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Automated merge with ssh://hg@m5sim.org/m5

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This commit is contained in:
Derek Hower 2010-01-25 11:53:06 -06:00
parent 5b90934dd2 5a4ebd6d12
commit cf08b232ff
6 changed files with 6 additions and 6 deletions
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2
tests/configs/o3-timing-mp-ruby.py
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@ -34,7 +34,7 @@ nb_cores = 4
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
import ruby_config
ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())

2
tests/configs/o3-timing-ruby.py
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@ -32,7 +32,7 @@ m5.util.addToPath('../configs/common')
import ruby_config
ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1)
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
cpu = DerivO3CPU(cpu_id=0)
cpu.clock = '2GHz'

2
tests/configs/simple-atomic-mp-ruby.py
View file

@ -34,7 +34,7 @@ nb_cores = 4
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
import ruby_config
ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())

2
tests/configs/simple-atomic-ruby.py
View file

@ -30,7 +30,7 @@ import m5
from m5.objects import *
import ruby_config
ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1)
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
system = System(cpu = AtomicSimpleCPU(cpu_id=0),
physmem = ruby_memory,

2
tests/configs/simple-timing-mp-ruby.py
View file

@ -33,7 +33,7 @@ nb_cores = 4
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
import ruby_config
ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())

2
tests/configs/simple-timing-ruby.py
View file

@ -30,7 +30,7 @@ import m5
from m5.objects import *
import ruby_config
ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1)
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
cpu = TimingSimpleCPU(cpu_id=0)
system = System(cpu = cpu,