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Gabe Black d3ed32b989 MIPS: Create an artificial control register to hold the thread pointer.
In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.

The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
2009-12-31 15:30:50 -05:00
build_opts ARM: Boilerplate full-system code. 2009-11-17 18:02:08 -06:00
configs X86: Record the memory mode when building an X86 system. 2009-12-19 01:49:34 -08:00
ext ply: update PLY to version 3.2 2009-08-16 13:39:58 -07:00
src MIPS: Create an artificial control register to hold the thread pointer. 2009-12-31 15:30:50 -05:00
tests m5: refreshed the ruby memtest regression stats 2009-11-18 18:00:41 -08:00
util regress: add POWER to regressions 2009-10-28 11:56:43 -07:00
.hgignore m5: Added the default m5out directory to the hg ignore list 2009-11-18 16:34:32 -08:00
.hgtags Added tag m5_2.0_beta6 for changeset d8b246a665c1 2008-10-09 02:20:16 -04:00
AUTHORS RELEASE: More changes to text 2007-11-01 21:07:49 -04:00
LICENSE Update copyright dates 2008-02-11 12:35:28 -05:00
README Update the README and RELEASE_NOTES files to prepare for beta 6. 2008-10-07 00:53:25 -04:00
RELEASE_NOTES Update the README and RELEASE_NOTES files to prepare for beta 6. 2008-10-07 00:53:25 -04:00
SConstruct arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00

This is release 2.0_beta6 of the M5 simulator.

For detailed information about building the simulator and getting
started please refer to http://www.m5sim.org.

Specific pages of interest are:
http://www.m5sim.org/wiki/index.php/Compiling_M5
http://www.m5sim.org/wiki/index.php/Running_M5

Short version:

1. If you don't have SCons version 0.96.91 or newer, get it from
http://wwww.scons.org.

2. If you don't have SWIG version 1.3.28 or newer, get it from
http://wwww.swig.org.

3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'.  This
will build the debug version of the m5 binary (m5.debug) for the Alpha
syscall emulation target, and run the quick regression tests on it.

If you have questions, please send mail to m5-users@m5sim.org

WHAT'S INCLUDED (AND NOT)
-------------------------

The basic source release includes these subdirectories:
 - m5: 
   - src: source code of the m5 simulator
   - tests: regression tests
   - ext: less-common external packages needed to build m5

To run full-system simulations, you will need compiled console,
PALcode, and kernel binaries and one or more disk images.  These files
are collected in a separate archive, m5_system.tar.bz2.  This file
can he downloaded separately.

M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
Tru64 version of Unix. We are able to distribute Linux and FreeBSD
bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-users@m5sim.org