Automated merge with ssh://hsul@localhost:4444//repo/m5

src/cpu/base.hh

@@ -274,7 +274,7 @@ class BaseCPU : public MemObject
      */
     virtual BranchPred *getBranchPred() { return NULL; };
 
-    virtual Counter totalInstructions() const { return 0; }
+    virtual Counter totalInstructions() const = 0;
 
     // Function tracing
   private:

src/mem/cache/cache_impl.hh

@@ -266,7 +266,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
         return false;
     }
 
-    blk = tags->accessBlock(pkt->getAddr(), lat);
+    int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+    blk = tags->accessBlock(pkt->getAddr(), lat, id);
 
     DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
             pkt->req->isInstFetch() ? " (ifetch)" : "",
@@ -299,7 +300,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
                 incMissCount(pkt);
                 return false;
             }
-            tags->insertBlock(pkt->getAddr(), blk);
+            int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+            tags->insertBlock(pkt->getAddr(), blk, id);
             blk->status = BlkValid | BlkReadable;
         }
         std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
@@ -976,7 +978,8 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
             tempBlock->tag = tags->extractTag(addr);
             DPRINTF(Cache, "using temp block for %x\n", addr);
         } else {
-            tags->insertBlock(addr, blk);
+            int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+            tags->insertBlock(pkt->getAddr(), blk, id);
         }
     } else {
         // existing block... probably an upgrade

src/mem/cache/tags/fa_lru.cc

@@ -154,7 +154,7 @@ FALRU::invalidateBlk(FALRU::BlkType *blk)
 }
 
 FALRUBlk*
-FALRU::accessBlock(Addr addr, int &lat, int *inCache)
+FALRU::accessBlock(Addr addr, int &lat, int context_src, int *inCache)
 {
     accesses++;
     int tmp_in_cache = 0;
@@ -228,7 +228,7 @@ FALRU::findVictim(Addr addr, PacketList &writebacks)
 }
 
 void
-FALRU::insertBlock(Addr addr, FALRU::BlkType *blk)
+FALRU::insertBlock(Addr addr, FALRU::BlkType *blk, int context_src)
 {
 }
 

src/mem/cache/tags/fa_lru.hh

@@ -182,7 +182,7 @@ public:
      * @param inCache The FALRUBlk::inCache flags.
      * @return Pointer to the cache block.
      */
-    FALRUBlk* accessBlock(Addr addr, int &lat, int *inCache = 0);
+    FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache = 0);
 
     /**
      * Find the block in the cache, do not update the replacement data.
@@ -200,7 +200,7 @@ public:
      */
     FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
 
-    void insertBlock(Addr addr, BlkType *blk);
+    void insertBlock(Addr addr, BlkType *blk, int context_src);
 
     /**
      * Return the hit latency of this cache.

src/mem/cache/tags/iic.cc

@@ -219,7 +219,7 @@ IIC::regStats(const string &name)
 
 
 IICTag*
-IIC::accessBlock(Addr addr, int &lat)
+IIC::accessBlock(Addr addr, int &lat, int context_src)
 {
     Addr tag = extractTag(addr);
     unsigned set = hash(addr);
@@ -338,7 +338,7 @@ IIC::findVictim(Addr addr, PacketList &writebacks)
 }
 
 void
-IIC::insertBlock(Addr addr, BlkType* blk)
+IIC::insertBlock(Addr addr, BlkType* blk, int context_src)
 {
 }
 

src/mem/cache/tags/iic.hh

@@ -422,7 +422,7 @@ class IIC : public BaseTags
      * @param lat The access latency.
      * @return A pointer to the block found, if any.
      */
-    IICTag* accessBlock(Addr addr, int &lat);
+    IICTag* accessBlock(Addr addr, int &lat, int context_src);
 
     /**
      * Find the block, do not update the replacement data.
@@ -440,7 +440,7 @@ class IIC : public BaseTags
      */
     IICTag* findVictim(Addr addr, PacketList &writebacks);
 
-    void insertBlock(Addr addr, BlkType *blk);
+    void insertBlock(Addr addr, BlkType *blk, int context_src);
 
     /**
      * Called at end of simulation to complete average block reference stats.

src/mem/cache/tags/lru.cc

@@ -150,7 +150,7 @@ LRU::~LRU()
 }
 
 LRUBlk*
-LRU::accessBlock(Addr addr, int &lat)
+LRU::accessBlock(Addr addr, int &lat, int context_src)
 {
     Addr tag = extractTag(addr);
     unsigned set = extractSet(addr);
@@ -200,7 +200,7 @@ LRU::findVictim(Addr addr, PacketList &writebacks)
 }
 
 void
-LRU::insertBlock(Addr addr, LRU::BlkType *blk)
+LRU::insertBlock(Addr addr, LRU::BlkType *blk, int context_src)
 {
     if (!blk->isTouched) {
         tagsInUse++;

src/mem/cache/tags/lru.hh

@@ -172,7 +172,7 @@ public:
      * @param lat The access latency.
      * @return Pointer to the cache block if found.
      */
-    LRUBlk* accessBlock(Addr addr, int &lat);
+    LRUBlk* accessBlock(Addr addr, int &lat, int context_src);
 
     /**
      * Finds the given address in the cache, do not update replacement data.
@@ -197,7 +197,7 @@ public:
      * @param addr The address to update.
      * @param blk The block to update.
      */
-     void insertBlock(Addr addr, BlkType *blk);
+     void insertBlock(Addr addr, BlkType *blk, int context_src);
 
     /**
      * Generate the tag from the given address.

src/mem/page_table.cc

@@ -222,6 +222,16 @@ PageTable::unserialize(Checkpoint *cp, const std::string &section)
         entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
         pTable[vaddr] = *entry;
         ++i;
-   }
+    }
+
+    process->M5_pid = pTable[vaddr].asn;
+
+#if THE_ISA == ALPHA_ISA
+    // The IPR_DTB_ASN misc reg must be set in Alpha for the tlb to work 
+    // correctly
+    int id = process->contextIds[0];
+    ThreadContext *tc = process->system->getThreadContext(id);
+    tc->setMiscRegNoEffect(IPR_DTB_ASN, process->M5_pid << 57);
+#endif
 }
 

src/sim/faults.cc

@@ -40,7 +40,7 @@
 #if !FULL_SYSTEM
 void FaultBase::invoke(ThreadContext * tc)
 {
-    fatal("fault (%s) detected @ PC %p", name(), tc->readPC());
+    panic("fault (%s) detected @ PC %p", name(), tc->readPC());
 }
 #else
 void FaultBase::invoke(ThreadContext * tc)
@@ -54,7 +54,7 @@ void FaultBase::invoke(ThreadContext * tc)
 
 void UnimpFault::invoke(ThreadContext * tc)
 {
-    fatal("Unimpfault: %s\n", panicStr.c_str());
+    panic("Unimpfault: %s\n", panicStr.c_str());
 }
 
 #if !FULL_SYSTEM

src/sim/serialize.cc

@@ -422,7 +422,7 @@ Serializable::serializeAll(const string &cpt_dir)
     time_t t = time(NULL);
     if (!outstream.is_open())
         fatal("Unable to open file %s for writing\n", cpt_file.c_str());
-    outstream << "// checkpoint generated: " << ctime(&t);
+    outstream << "## checkpoint generated: " << ctime(&t);
 
     globals.serialize(outstream);
     SimObject::serializeAll(outstream);

util/checkpoint-aggregator.py

@@ -0,0 +1,139 @@
+#! /usr/bin/env python2.6
+
+from ConfigParser import ConfigParser
+import gzip
+
+import sys, re, optparse, os
+
+class myCP(ConfigParser):
+    def __init__(self):
+        ConfigParser.__init__(self)
+
+    def optionxform(self, optionstr):
+        return optionstr
+
+def aggregate(options, args):
+    merged = myCP()
+    page_ptr = 0
+
+    allfiles = os.listdir(os.getcwd())
+    cpts = []
+    for arg in args:
+        found = False
+        for f in allfiles:
+            if re.compile("cpt." + arg + ".\d+").search(f):
+                found = True
+                cpts.append(f)
+                break
+        if not found:
+            print "missing checkpoint: ", arg
+            sys.exit(1)
+
+    dirname = "-".join([options.prefix, "cpt"])
+    print dirname
+    agg_name = "-".join(args)
+    print agg_name
+    fullpath = os.path.join("..", dirname, "cpt." + agg_name + ".10000")
+    if not os.path.isdir(fullpath):
+        os.system("mkdir -p " + fullpath)
+
+    myfile = open(fullpath + "/system.physmem.physmem", "wb+")
+    merged_mem = gzip.GzipFile(fileobj=myfile, mode="wb")
+
+    max_curtick = 0
+    when = 0
+    for (i, arg) in enumerate(args):
+        config = myCP()
+        config.readfp(open(cpts[i] + "/m5.cpt"))
+
+        for sec in config.sections():
+            if re.compile("cpu").search(sec):
+                newsec = re.sub("cpu", "cpu" + str(i), sec)
+                merged.add_section(newsec)
+
+                items = config.items(sec)
+                for item in items:
+                    if item[0] == "ppn":
+                        if config.getint(sec, "tag") != 0:
+                            merged.set(newsec, item[0], int(item[1]) + page_ptr)
+                            continue
+                    elif item[0] == "asn":
+                        tmp = re.compile("(.*).Entry(\d+)").search(sec).groups()
+                        if config.has_option(tmp[0], "nlu"):
+                            size = config.getint(tmp[0], "nlu")
+                            if int(tmp[1]) < size:
+                                merged.set(newsec, item[0], i)
+                                continue
+                        else:
+                            merged.set(newsec, item[0], i)
+                            continue
+                    merged.set(newsec, item[0], item[1])
+            elif sec == "system":
+                pass
+            elif sec == "Globals":
+                tick = config.getint(sec, "curTick")
+                if tick > max_curtick:
+                    max_curtick = tick
+                    when = config.getint("system.cpu.tickEvent", "_when")
+            else:
+                if i == 0:
+                    print sec
+                    merged.add_section(sec)
+                    for item in config.items(sec):
+                        merged.set(sec, item[0], item[1])
+                        if item[0] == "curtick":
+                            merged.optionxform(str("curTick"))
+                        elif item[0] == "numevents":
+                            merged.optionxform(str("numEvents"))
+
+        page_ptr = page_ptr + int(config.get("system", "page_ptr"))
+
+        ### memory stuff
+        f = open(cpts[i] + "/system.physmem.physmem", "rb")
+        gf = gzip.GzipFile(fileobj=f, mode="rb")
+        bytes = int(config.get("system", "page_ptr")) << 13
+        print "bytes to be read: ", bytes
+
+        bytesRead = gf.read(int(config.get("system", "page_ptr")) << 13)
+        merged_mem.write(bytesRead)
+
+        gf.close()
+        f.close()
+
+    merged.add_section("system")
+    merged.set("system", "page_ptr", page_ptr)
+    print "WARNING: "
+    print "Make sure the simulation using this checkpoint has at least "
+    if page_ptr > (1<<20):
+        print "8G ",
+    elif page_ptr > (1<<19):
+        print "4G ",
+    elif page_ptr > (1<<18):
+        print "2G ",
+    elif page_ptr > (1<<17):
+        print "1G ",
+    elif page_ptr > (1<<16):
+        print "512KB ",
+    else:
+        print "this is a small sim, you're probably fine",
+    print "of memory."
+
+    merged.add_section("Globals")
+    merged.set("Globals", "curTick", max_curtick)
+
+    for i in xrange(len(args)):
+        merged.set("system.cpu" + str(i) + ".tickEvent", "_when", when)
+
+    merged.write(file(fullpath + "/m5.cpt", "wb"))
+    merged_mem.close()
+    myfile.close()
+
+if __name__ == "__main__":
+
+    parser = optparse.OptionParser()
+    parser.add_option("--prefix", type="string", default="agg")
+
+    (options, args) = parser.parse_args()
+
+    aggregate(options, args)
+