Commit graph

7741 commits

Author SHA1 Message Date
Brad Beckmann 09854be558 config: Added the topology description to m5 config.ini 2010-08-20 11:46:11 -07:00
Brad Beckmann c7bd896448 ruby: added token broadcast config params to cmd options 2010-08-20 11:46:11 -07:00
Brad Beckmann 5c801090a3 config: reorganized how ruby specifies command-line options 2010-08-20 11:44:09 -07:00
Brad Beckmann eb1e5636e3 ruby: Fixed printout when Sequencer detects a deadlock 2010-08-20 11:41:35 -07:00
Brad Beckmann d7d73680c4 MESI_CMP_directory: bug fix for old PUTX requests 2010-08-20 11:41:35 -07:00
Brad Beckmann 7816d0d12b config: moved python protocol config files
Moved the python protocol config files back to their original location to avoid
addToPath calls.

--HG--
rename : configs/ruby/protocols/MESI_CMP_directory.py => configs/ruby/MESI_CMP_directory.py
rename : configs/ruby/protocols/MI_example.py => configs/ruby/MI_example.py
rename : configs/ruby/protocols/MOESI_CMP_directory.py => configs/ruby/MOESI_CMP_directory.py
rename : configs/ruby/protocols/MOESI_CMP_token.py => configs/ruby/MOESI_CMP_token.py
rename : configs/ruby/protocols/MOESI_hammer.py => configs/ruby/MOESI_hammer.py
2010-08-20 11:41:35 -07:00
Steve Reinhardt e0754c0f6c misc: add some AMD copyright notices
Meant to add these with the previous batch of csets.
2010-08-17 05:49:05 -07:00
Steve Reinhardt 164a211f10 x86: minor checkpointing bug fixes 2010-08-17 05:20:39 -07:00
Steve Reinhardt f064aa3060 sim: revamp unserialization procedure
Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in both ckpt and non-ckpt
cases.

If restoring from a checkpoint, loadState(ckpt) is called on each
SimObject.  The default implementation simply calls unserialize() if
there is a corresponding checkpoint section, so we get backward
compatibility for existing objects.  However, objects can override
loadState() to get other behaviors, e.g., doing other programmed
initializations after unserialize(), or complaining if no checkpoint
section is found.  (Note that the default warning for a missing
checkpoint section is now gone.)

If not restoring from a checkpoint, we call the new initState() method
on each SimObject instead.  This provides a hook for state
initializations that are only required when *not* restoring from a
checkpoint.

Given this new framework, do some cleanup of LiveProcess subclasses
and X86System, which were (in some cases) emulating initState()
behavior in startup via a local flag or (in other cases) erroneously
doing initializations in startup() that clobbered state loaded earlier
by unserialize().
2010-08-17 05:17:06 -07:00
Steve Reinhardt 2519d116c9 sim: fold checkpoint restore code into instantiate()
The separate restoreCheckpoint() call is gone; just pass
the checkpoint dir as an optional arg to instantiate().
This change is a precursor to some more extensive
reworking of the startup code.
2010-08-17 05:17:06 -07:00
Steve Reinhardt cfaddd5fd3 configs: clean up checkpoint code in Simulation.py
Small change to clean up some redundant code.
Should not have any functional impact.
2010-08-17 05:17:06 -07:00
Steve Reinhardt 5577048bcf test: Update stats for python object iteration.
Small changes in tests with data races due to new object creation
order.
2010-08-17 05:14:03 -07:00
Steve Reinhardt c2e1458746 sim: clean up child handling
The old code for handling SimObject children was kind of messy,
with children stored both in _values and _children, and
inconsistent and potentially buggy handling of SimObject
vectors.  Now children are always stored in _children, and
SimObject vectors are consistently handled using the
SimObjectVector class.

Also, by deferring the parenting of SimObject-valued parameters
until the end (instead of doing it at assignment), we eliminate
the hole where one could assign a vector of SimObjects to a
parameter then append to that vector, with the appended objects
never getting parented properly.

This patch induces small stats changes in tests with data races
due to changes in the object creation & initialization order.
The new code does object vectors in order and so should be more
stable.
2010-08-17 05:11:00 -07:00
Steve Reinhardt 5ea906ba16 sim: move iterating over SimObjects into Python. 2010-08-17 05:08:50 -07:00
Steve Reinhardt c2cce96a0b sim: fail on implicit creation of orphans via ports
Orphan SimObjects (not in the config hierarchy) could get
created implicitly if they have a port connection to a SimObject
that is in the hierarchy.  This means that there are objects on
the C++ SimObject list (created via the C++ SimObject
constructor call) that are unknown to Python and will get
skipped if we walk the hierarchy from the Python side (as we are
about to do).  This patch detects this situation and prints an
error message.

Also fix the rubytester config script which happened to rely on
this behavior.
2010-08-17 05:06:22 -07:00
Steve Reinhardt 1fbe466345 sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once.  The C++ Root object already panics if more than one is
created.  This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists).  It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone.  Users who use
configs/common/Simulate.py should not notice.
2010-08-17 05:06:22 -07:00
Steve Reinhardt 0f8b5afd7a tests: update reference config.ini files for previous cset
Rename 'responder_set' to 'use_default_range'.
2010-08-17 05:06:22 -07:00
Steve Reinhardt 0685ae7a2d bus: clean up default responder code.
Clean up some minor things left over from the default responder
change in rev 9af6fb59752f.  Mostly renaming the 'responder_set'
param to 'use_default_range' to actually reflect what it does...
old name wasn't that descriptive in the first place, but now
it really doesn't make sense at all.

Also got rid of the bogus obsolete assignment to 'bus.responder'
which used to be a parameter but now is interpreted as an
implicit child assignment, and which was giving me problems in
the config restructuring to come.  (A good argument for not
allowing implicit child assignments, IMO, but that's water under
the bridge, I'm afraid.)

Also moved the Bus constructor to the .cc file since that's
where it should have been all along.
2010-08-17 05:06:21 -07:00
Gabe Black c4ba6967a5 Inorder: Fix compilation of m5.fast.
printMemData is only used in DPRINTFs. If those are removed by compiling
m5.fast, that function is unused, gcc generates a warning, that gets turned
into an error, and the build fails. This change surrounds the function
definition with #if TRACING_ON so it only gets compiled in if the DPRINTFs do
to.
2010-08-14 01:00:45 -07:00
Gabe Black 961aafc044 Merge with head. 2010-08-13 06:16:30 -07:00
Gabe Black aa8c6e9c95 CPU: Add readBytes and writeBytes functions to the exec contexts. 2010-08-13 06:16:02 -07:00
Gabe Black 65dbcc6ea1 InOrder: Clean up some DPRINTFs that print data sent to/from the cache. 2010-08-13 06:16:00 -07:00
Gabe Black 52a90a5998 CPU: Tidy up endianness handling for mmapped "IPR"s. 2010-08-13 06:10:45 -07:00
Joel Hestness 73d9a51835 util/m5/m5.c: ensure readfile() buffer pages are in page table
(and marked dirty, in case that matters) by touching them beforehand
2010-08-12 17:16:04 -07:00
Joel Hestness 53c241fc16 TimingSimpleCPU: fix NO_ACCESS memory op handling
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op
doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs
to handle the case where the current status of the CPU is Running
and not DcacheWaitResponse or DTBWaitResponse
2010-08-12 17:16:02 -07:00
Nathan Binkert 2e9e75447a None, not none 2010-08-08 22:57:16 -07:00
Steve Reinhardt 545a6fcd04 .hgignore: added src/doxygen 2010-07-27 20:00:38 -07:00
Ali Saidi 1b73376b0b ARM: Add regression tests 2010-07-27 01:03:44 -04:00
Timothy M. Jones 97d245278d Power: The condition register should be set or cleared upon a system call
return to indicate success or failure.
2010-07-22 18:54:37 +01:00
Timothy M. Jones 607f519800 LSQ Unit: After deleting part of a split request, set it to NULL so that it
isn't accidentally deleted again later (causing a segmentation fault).
2010-07-22 18:54:37 +01:00
Timothy M. Jones 28a5ea3f99 Port: Only indicate that a SimpleTimingPort is drained if its send event is
not scheduled, as well as the transmit list being empty.
2010-07-22 18:54:37 +01:00
Timothy M. Jones e50a880297 O3CPU: Fix a bug where stores in the cpu where never marked as split. 2010-07-22 18:52:02 +01:00
Timothy M. Jones 0d301ca4c4 Syscall: Don't close the simulator's standard file descriptors. 2010-07-22 18:47:52 +01:00
Timothy M. Jones 9a3533ec84 O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly
switching between O3 and another CPU, O3's tick event might still be scheduled
in the event queue (as squashed).  Therefore, check for a squashed tick event
as well as a non-scheduled event when taking over from another CPU and deal
with it accordingly.
2010-07-22 18:47:43 +01:00
Timothy M. Jones 8c76715979 Power: Provide a utility function to copy registers from one thread context
to another in the Power ISA.
2010-07-22 18:47:03 +01:00
Nathan Binkert 21bf6ff101 stats: unify the two stats distribution type better 2010-07-21 18:54:53 -07:00
Nathan Binkert 2a1309f213 stats: cleanup a few small problems in stats 2010-07-21 15:53:53 -07:00
Nathan Binkert 76c92c3e30 python: add a sorted dictionary class
It would be nice if python had a tree class that would do this for real,
but since we don't, we'll just keep a sorted list of keys and update
it on demand.
2010-07-21 15:53:53 -07:00
Nathan Binkert 3518416917 python: Add mechanism to override code compiled into the exectuable
If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to
True, then imports that would normally find python code compiled into
the executable will instead first check in the absolute location where
the code was found during the build of the executable.  This only
works for files in the src (or extras) directories, not automatically
generated files.

This is a developer feature!
2010-07-21 15:53:52 -07:00
Tushar Krishna 11bb678a80 Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses 2010-07-21 09:55:57 -07:00
Steve Reinhardt 262b2e2b94 SimObject: transparently forward Python attribute refs to C++.
This tidbit was pulled from a larger patch for Tim's sake, so
the comment reflects functions that haven't been exported yet.
I hope to commit them soon so it didn't seem worth cleaning up.
2010-07-17 08:56:49 -07:00
Gabe Black 8cec870568 ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault. 2010-07-15 02:11:56 -07:00
Gabe Black 4e3183cb1e ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index. 2010-07-13 22:41:47 -07:00
Steve Reinhardt 897247d63b cache: fix bug in SC upgrade handling
This bug was introduced with the recent rework of SC
failure handling in cset f97b62be544f.
2010-07-08 17:56:13 -07:00
Brad Beckmann a03c1cd6e0 garnet: Added topology print function to Garnet printStats 2010-07-08 16:18:20 -07:00
Tushar Krishna 2f2962fee3 NetworkMessage copy constructor fix 2010-07-08 16:18:20 -07:00
Steve Reinhardt 26f5a9c2cb checkpointing: another small overload fix
On Nate's advice, overload 'char' as well as 'signed char'
and 'unsigned char'.
2010-07-05 22:57:23 -07:00
Steve Reinhardt 387cbffb7a sim: allow SimObject subclasses to define classmethods
(without requiring a leading underscore)
Also a little cleanup on type names in SimObject.py.
2010-07-05 21:39:38 -07:00
Steve Reinhardt 30ce620d1d sim: fold StartupCallback into SimObject
There used to be a reason to have StartupCallback
be a separate object, but not any more.  Now
it's just confusing.
2010-07-05 21:39:38 -07:00
Steve Reinhardt 345dfd1b41 checkpointing: minor cleanup.
Move some static checkpoint stuff into the
Checkpoint object namespace.
2010-07-05 21:39:38 -07:00