Commit graph

9614 commits

Author SHA1 Message Date
Andreas Hansson
08f7a8bc00 stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
2013-03-26 14:46:49 -04:00
Andreas Hansson
93a8423dea mem: Separate waiting for the bus and waiting for a peer
This patch splits the retryList into a list of ports that are waiting
for the bus itself to become available, and a map that tracks the
ports where forwarding failed due to a peer not accepting the
packet. Thus, when a retry reaches the bus, it can be sent to the
appropriate port that initiated that transaction.

As a consequence of this patch, only ports that are really ready to go
will get a retry, thus reducing the amount of redundant failed
attempts. This patch also makes it easier to reason about the order of
servicing requests as the ports waiting for the bus are now clearly
FIFO and much easier to change if desired.
2013-03-26 14:46:47 -04:00
Andreas Hansson
362f6f1a16 mem: Introduce a variable for the retrying port
This patch introduces a variable to keep track of the retrying port
instead of relying on it being the front of the retryList.

Besides the improvement in readability, this patch is a step towards
separating out the two cases where a port is waiting for the bus to be
free, and where the forwarding did not succeed and the bus is waiting
for a retry to pass on to the original initiator of the transaction.

The changes made are currently such that the regressions are not
affected. This is ensured by always prioritizing the currently
retrying port and putting it back at the front of the retry list.
2013-03-26 14:46:46 -04:00
Andreas Hansson
2123176684 mem: Add a generic id field to the packet trace
This patch adds an optional generic 64-bit identifier field to the
packet trace. This can be used to store the sequential number of the
instruction that gave rise to the packet, thread id, master id,
"sub"-master within a larger module etc. As the field is optional it
has a marginal cost if not used.
2013-03-26 14:46:45 -04:00
Andreas Hansson
7a57b1bce0 mem: Add optional request flags to the packet trace
This patch adds an optional flags field to the packet trace to encode
the request flags that contain information about whether the request
is (un)cacheable, instruction fetch, preftech etc.
2013-03-26 14:46:44 -04:00
Andreas Hansson
08c1835bef cpu: Remove CpuPort and use MasterPort in the CPU classes
This patch changes the port in the CPU classes to use MasterPort
instead of the derived CpuPort. The functions of the CpuPort are now
distributed across the relevant subclasses. The port accessor
functions (getInstPort and getDataPort) now return a MasterPort
instead of a CpuPort. This simplifies creating derivative CPUs that do
not use the CpuPort.
2013-03-26 14:46:42 -04:00
Andreas Sandberg
670fc52f18 x86: Revert [02321b16685f] which breaks m5ops on x86
Changeset 02321b16685f added m5_writefile to m5op_x86.S a second time,
which causes a compilation error on when compiling for x86. This
changeset reverts that changeset and fixes the error.
2013-03-25 13:20:15 +01:00
Nilay Vaish
546ffb2d6d config: return exit event instead of cause
changeset: a4739b6f799d made some changes that where an exit event
should have been returned in place of exit cause. This patch corrects
the error.
2013-03-22 17:31:24 -05:00
Nilay Vaish
04fe6b486a regressions: updates to config.ini for ruby tests 2013-03-22 17:21:25 -05:00
Nilay Vaish
b2c8c50f17 ruby: slicc: set sender, receiver clock objs for optional queue 2013-03-22 17:21:23 -05:00
Nilay Vaish
e85b556d70 ruby: message buffer: correct previous errors
A recent set of patches added support for multiple clock domains to ruby.
I had made some errors while writing those patches. The sender was using
the receiver side clock while enqueuing a message in the buffer. Those
errors became visible while creating (or restoring from) checkpoints. The
errors also become visible when a multi eventq scenario occurs.
2013-03-22 17:21:22 -05:00
Nilay Vaish
47c8cb72fc ruby: message buffer: remove _ptr from some variables
The names were getting too long.
2013-03-22 15:53:27 -05:00
Nilay Vaish
6465cf5824 ruby: message buffer node: used Tick in place of Cycles
The message buffer node used to keep time in terms of Cycles. Since the
sender and the receiver can have different clock periods, storing node
time in cycles requires some conversion. Instead store the time directly
in Ticks.
2013-03-22 15:53:26 -05:00
Nilay Vaish
39e9445468 ruby: consumer: avoid using receiver side clock
A set of patches was recently committed to allow multiple clock domains
in ruby. In those patches, I had inadvertently made an incorrect use of
the clocks. Suppose object A needs to schedule an event on object B. It
was possible that A accesses B's clock to schedule the event. This is not
possible in actual system. Hence, changes are being to the Consumer class
so as to avoid such happenings. Note that in a multi eventq simulation,
this can possibly lead to an incorrect simulation.

There are two functions in the Consumer class that are used for scheduling
events. The first function takes in the relative delay over the current time
as the argument and adds the current time to it for scheduling the event.
The second function takes in the absolute time (in ticks) for scheduling the
event. The first function is now being moved to protected section of the
class so that only objects of the derived classes can use it. All other
objects will have to specify absolute time while scheduling an event
for some consumer.
2013-03-22 15:53:26 -05:00
Nilay Vaish
28005a7626 ruby: remove unsued profile functions 2013-03-22 15:53:25 -05:00
Nilay Vaish
89bb826079 ruby: keep histogram of outstanding requests in seq
The histogram for tracking outstanding counts per cycle is maintained
in the profiler. For a parallel implementation of the memory system, we
need that this histogram is maintained locally. Hence it will now be
kept in the sequencer itself. The resulting histograms will be merged
when the stats are printed.
2013-03-22 15:53:25 -05:00
Nilay Vaish
870d545788 slicc: remove check if the L1Cache has a sequencer 2013-03-22 15:53:24 -05:00
Nilay Vaish
8573a69d8f ruby: move stall and wakeup functions to AbstractController
These functions are currently implemented in one of the files related to Slicc.
Since these are purely C++ functions, they are better suited to be in the base
class.
2013-03-22 15:53:24 -05:00
Nilay Vaish
eccc86e809 ruby: connect two controllers using only message buffers
This patch modifies ruby so that two controllers can be connected to each
other with only message buffers in between. Before this patch, all the
controllers had to be connected to the network  for them to communicate
with each other. With this patch, one can have protocols where a controller
is not connected to the network, but communicates with another controller
through a message buffer.
2013-03-22 15:53:23 -05:00
Nilay Vaish
5aa43e130a ruby: convert Topology to regular class
The Topology class in Ruby does not need to inherit from SimObject class.
This patch turns it into a regular class. The topology object is now created
in the constructor of the Network class. All the parameters for the topology
class have been moved to the network class.
2013-03-22 15:53:23 -05:00
Nilay Vaish
2d50127642 ruby: network: move routers from topology to network 2013-03-22 15:53:22 -05:00
Andreas Hansson
2ca42cd626 cpu: Avoid including inorder TLBUnit to avoid gcc LTO bug
This patch comments out the inclusion of the inorder TLBUnit which is
only used in the 9-stage pipeline. With the TLBUnit present, gcc >=
4.6 in combination with LTO ends up throwing away the definition of
the TLBUnit destructor, and consequently fail to link. See
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53808 for more details
about the bug, and http://gcc.gnu.org/ml/gcc/2012-06/msg00397.html for
the discussion thread that also touches on similar issues seen with
clang.
2013-03-20 06:41:23 -04:00
Andreas Sandberg
e28e6246fc scons: Try to use 'tcmalloc' before 'tcmalloc_minimal'
tcmalloc_minimal doesn't support the heap checker on Debian, while
tcmalloc does. Instead of always linking with tcmalloc_minimal, if it
exists, we first check for tcmalloc and then use tcmalloc_minimal as a
fallback.
2013-03-18 11:24:56 +01:00
Andreas Sandberg
468ad10f50 scons: Avoid malloc/free compiler optimization when using tcmalloc
According to the tcmalloc readme, the recommended way of compiling
applications that make use of tcmalloc is to disable compiler
optimizations that make assumptions about malloc and friends. This
changeset adds the necessary compiler flags for both gcc and clang.

From the tcmalloc readme:
"NOTE: When compiling with programs with gcc, that you plan to link
with libtcmalloc, it's safest to pass in the flags

 -fno-builtin-malloc -fno-builtin-calloc
 -fno-builtin-realloc -fno-builtin-free

when compiling."
2013-03-18 10:57:26 +01:00
Andreas Sandberg
9e9a47cb9a scons: Don't explicitly add tcmalloc_minimal to LIBS
SCons automatically adds a library to LIBS if conf.CheckLib succeeds,
so there is no need to explicitly add the library.
2013-03-18 10:44:34 +01:00
Andreas Sandberg
3e3475138b scons: Include flags required to link statically with Python
Python requires the flags in LINKFORSHARED to be added the linker
flags when linking with a statically with Python. Failing to do so can
lead to errors from the Python's dynamic module loader at start up.

--HG--
extra : rebase_source : e7a8daf72f4ede7ee5a4a5398a0b12e978a919b9
2013-03-18 10:22:21 +01:00
Andreas Hansson
c01c5e971b mem: Fix missing delete of packet in DRAM access
This patch fixes a memory leak caused by not deleting packets that
require no response.
2013-03-18 05:22:45 -04:00
Nilay Vaish
dc37b03439 ruby: set: corrects csprintf() call introduced by 7d95b650c9b6 2013-03-15 16:28:08 -05:00
Andreas Sandberg
9544e8fbe0 scons: Check for known buggy version of SWIG (2.0.9)
SWIG version 2.0.9 uses fully qualified module names despite of the
importing module being in the same package as the imported
module. This has the unfortunate consequence of causing the following
error when importing m5.internal.event:

Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "src/python/importer.py", line 75, in load_module
    exec code in mod.__dict__
  File "src/python/m5/__init__.py", line 35, in <module>
    import internal
  File "src/python/importer.py", line 75, in load_module
    exec code in mod.__dict__
  File "src/python/m5/internal/__init__.py", line 32, in <module>
    import event
  File "src/python/importer.py", line 75, in load_module
    exec code in mod.__dict__
  File "build/X86/python/swig/event.py", line 107, in <module>
    class Event(m5.internal.serialize.Serializable):
AttributeError: 'module' object has no attribute 'internal'

When 'event' is loaded, it triggers 'serialize' to be loaded. However,
it seems like the dictionary of 'm5' isn't updated until after
__init__.py terminates, which means that 'event' never sees the
'internal' attribute on 'm5'. Older versions of SWIG didn't include
the fully qualified module name if the modules were in the same
package.
2013-03-14 16:08:55 +01:00
Andreas Sandberg
fc6f569d94 cpu: Fix state transition bug in the traffic generator
The traffic generator used to incorrectly determine the next state in
when state 0 had a non-zero probability. Due to the way the next
transition was determined, state 0 could never be entered other than
as an initial state. This changeset updates the transitition() method
to correctly handle such cases and cases where the transition matrix
is a 1x1 matrix.
2013-03-12 18:41:29 +01:00
Nilay Vaish
53a0597805 regressions: x86: stats updates due to new x87 insts 2013-03-11 17:45:09 -05:00
Nilay Vaish
5c940fec0a x86: implement some of the x87 instructions
This patch implements ftan, fprem, fyl2x, fld* floating-point instructions.
2013-03-11 13:15:46 -05:00
Andreas Hansson
82f600e02d base: Fix address range granularity calculations
This patch fixes a bug in the address range granularity
calculations. Previously it incorrectly used the high bit to establish
the size of the regions created, when it should really be looking at
the low bit.
2013-03-07 05:55:03 -05:00
Andreas Hansson
92e973b310 ruby: Fix gcc 4.8 maybe-uninitialized compilation error
This patch fixes the one-and-only gcc 4.8 compilation error, being a
warning about "maybe uninitialized" in Orion.
2013-03-07 05:55:02 -05:00
Andreas Hansson
c4645c0d68 x86: Make the table walker reset the packet delay
This patch fixes an issue related to the table walker recycling
packets that still have a bus delay that is not accounted for. For
now, we simply ignore the values and reset them to zero.
2013-03-07 05:55:01 -05:00
Nilay Vaish
d24d5446c5 regressions: stats updates due to no physmem in ruby 2013-03-06 21:57:10 -06:00
Nilay Vaish
c061819890 ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.
2013-03-06 21:53:57 -06:00
Nilay Vaish
e8802fa127 ruby: garnet: fixed: implement functional access 2013-03-06 21:53:16 -06:00
Ali Saidi
09b2430e95 stats: update patches for branch predictor and fetch updates. 2013-03-04 23:33:47 -05:00
Ali Saidi
f205d83359 cpu: fix a switching issue with the o3 cpu.
This change fixes the switcheroo test that broke earlier this month. The code
that was checking for the pipeline being blocked wasn't checking for a pending
translation, only for a icache access.
2013-03-04 23:33:47 -05:00
Ali Saidi
f4fd12d49e ARM: fix some cases where instructions that write to fp reg 15 are accidently branches. 2013-03-04 23:33:47 -05:00
Blake Hechtman ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
af8eb67fb4 ruby: fixes functional writes to RubyRequest
The functional write code was assuming that all writes are block sized,
which may not be true for Ruby Requests. This bug can lead to a buffer
overflow.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-03-02 23:12:55 -06:00
Nilay Vaish
a4e8512afa sim: remove duplicate check on stack size 2013-03-02 18:04:51 -06:00
Andreas Hansson
e5bcb30756 mem: Add check if SimpleDRAM nextReqEvent is scheduled
This check covers a case where a retry is called from the SimpleDRAM
causing a new request to appear before the DRAM itself schedules a
nextReqEvent. By adding this check, the event is not scheduled twice.
2013-03-01 13:20:33 -05:00
Andreas Hansson
da5356ccce mem: Add a method to build multi-channel DRAM configurations
This patch adds a class method that allows easy creation of
channel-interleaved multi-channel DRAM configurations. It is enabled
by a class method to allow customisation of the class independent of
the channel configuration. For example, the user can create a MyDDR
subclass of e.g. SimpleDDR3, and then create a four-channel
configuration of the subclass by calling MyDDR.makeMultiChannel(4,
mem_start, mem_size).
2013-03-01 13:20:32 -05:00
Andreas Hansson
cb9e208a4c stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
2013-03-01 13:20:30 -05:00
Andreas Hansson
0facc8e1ac mem: SimpleDRAM variable naming and whitespace fixes
This patch fixes a number of small cosmetic issues in the SimpleDRAM
module. The most important change is to move the accounting of
received packets to after the check is made if the packet should be
retried or not. Thus, packets are only counted if they are actually
accepted.
2013-03-01 13:20:24 -05:00
Andreas Hansson
3ba131f4d5 mem: Add support for multi-channel DRAM configurations
This patch adds support for multi-channel instances of the DRAM
controller model by stripping away the channel bits in the address
decoding. The patch relies on the availiability of address
interleaving and, at this time, it is up to the user to configure the
interleaving appropriately. At the moment it is assumed that the
channel interleaving bits are immediately following the column bits
(smallest sensible interleaving). Convenience methods for building
multi-channel configurations will be added later.
2013-03-01 13:20:22 -05:00
Andreas Hansson
1a58362e25 mem: Merge interleaved ranges when creating backing store
This patch adds merging of interleaved ranges before creating the
backing stores. The backing stores are always a contigous chunk of the
address space, and with this patch it is possible to have interleaved
memories in the system.
2013-03-01 13:20:21 -05:00
Andreas Hansson
cafd38f36c mem: Merge ranges in bus before passing them on
This patch adds basic merging of address ranges to the bus, such that
interleaved ranges are merged together before being passed on by the
bus. As such, the bus aggregates the address ranges of the connected
slave ports and then passes on the merged ranges through its master
ports. The bus thus hides the complexity of the interleaved ranges and
only exposes contigous ranges to the surrounding system.

As part of this patch, the bus ranges are also cached for any future
queries.
2013-03-01 13:20:19 -05:00