Commit graph

2843 commits

Author SHA1 Message Date
Kevin Lim
018ba50f2c Switch out fixes for CPUs.
src/cpu/o3/cpu.cc:
    Fix up keeping proper state when switched out and drained.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Keep track of the event we use to schedule fetch initially and upon resume.  We may have to cancel the event if the CPU is switched out.

--HG--
extra : convert_revision : 60a2a1bd2cdc67bd53ca4a67aa77166c826a4c8c
2006-07-07 15:38:15 -04:00
Kevin Lim
55e59e26c1 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 942c43e2fdd68cde7aaaba5e88a667f80feab162
2006-07-06 23:20:44 -04:00
Kevin Lim
6872b99c29 Be sure to call resume after restoring from a checkpoint.
--HG--
extra : convert_revision : 4d672917038779a23f4ce7eb5d4e3039c1f5d726
2006-07-06 23:16:22 -04:00
Kevin Lim
fff7531677 Support serializing and unserializing in the O3 CPU. Also a few small fixes for draining/switching CPUs.
src/cpu/o3/commit_impl.hh:
    Fix to clear drainPending variable on call to resume.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Support serializing and unserializing in the O3 CPU.
src/cpu/o3/lsq_impl.hh:
    Be sure to say we have no stores to write back if the active thread list is empty.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
    Slightly change how SimpleThread is used to copy from other ThreadContexts.

--HG--
extra : convert_revision : 92a5109b3783a989d5b451036061ef82c56d3121
2006-07-06 23:13:38 -04:00
Kevin Lim
fbe3e22474 Fix the O3CPU to support the multi-pass method for checking if the system has fully drained.
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
    Return a value so that the CPU can instantly return from draining if the pipeline is already drained.
src/cpu/o3/cpu.cc:
    Use values returned from pipeline stages so that the CPU can instantly return from draining if the pipeline is already drained.

--HG--
extra : convert_revision : d8ef6b811644ea67c8b40c4719273fa224105811
2006-07-06 17:57:20 -04:00
Kevin Lim
e7ccc94ea3 Various serialization changes to make it possible for the O3CPU to checkpoint.
src/arch/alpha/regfile.hh:
    Define serialize/unserialize functions on MiscRegFile itself.
src/cpu/o3/regfile.hh:
    Remove old commented code.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
    Push common serialization code to ThreadState level.  Also allow the SimpleThread to be used for checkpointing by other models.
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
    Move common serialization code into ThreadState.

--HG--
extra : convert_revision : ef64ef515355437439af967eda2e610e8c1b658b
2006-07-06 17:53:26 -04:00
Ron Dreslinski
1ccfdb442f Timing cache works for hello world test.
Still need
1) detailed CPU (blocking ability in cache)
1a) Multiple outstanding requests (need to keep track of times for events)
2)Multi-level support
3)MP coherece support
4)LL/SC support
5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu))

src/cpu/simple/timing.cc:
    Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
    Handle marking MSHR's in service
    Add support for getting CSHR's
src/mem/cache/base_cache.hh:
    Make these functions visible at the base cache level
src/mem/cache/cache.hh:
    make the functions virtual
src/mem/cache/cache_impl.hh:
    Rename the function to make sense
src/mem/packet.hh:
    Accidentally clearing the needsResponse field when sending a response back.

--HG--
extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2
2006-07-06 16:52:05 -04:00
Kevin Lim
8bf9709d91 Two minor FS compile fixes.
src/dev/tsunami_pchip.hh:
    Need ULL() for 32-bit hosts.
src/sim/pseudo_inst.cc:
    Forgot to remove sampler include from here.

--HG--
extra : convert_revision : 6ab6bdc721290167b4c2b78da3d28a4992eb24d5
2006-07-06 16:26:44 -04:00
Kevin Lim
8ae4f45bc4 Fixes for draining.
src/cpu/simple/timing.cc:
    Update for changed return values.
src/python/m5/__init__.py:
    Loop in order to make sure all objects are really drained.  Objects may become undrained as other objects become drained (e.g. a bus-bridge has a packet, while a bus is empty, and the first drain() will cause the bus-bridge to give the packet to the bus).

    The only case we know every object is actually drained is if they all return immediately that they are drained.

--HG--
extra : convert_revision : 80057a1d6d30381bd0b67b23549bd202f447c5cb
2006-07-06 16:06:00 -04:00
Ron Dreslinski
a1d208a65d Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 507eefde3514c35ca8420408cc89590d83cc6fc6
2006-07-06 15:16:15 -04:00
Ron Dreslinski
329e32f8c6 Now timing reads work in single level of cache with simple cpu
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
    Changes to handle timing reads in Simple CPU (blocking buffers)

--HG--
extra : convert_revision : a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f
2006-07-06 15:15:37 -04:00
Kevin Lim
c8a37ce715 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0c4fbbe0826358a6a58f844bec34ce830ffd4ced
2006-07-06 14:54:09 -04:00
Ali Saidi
4b74110071 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 4669e87d29fa3e0ca9009f6b9dce72113220d7bc
2006-07-06 14:41:09 -04:00
Ali Saidi
93839380e7 Add default responder to bus
Update configuration for new default responder on bus
Update to devices to handle their own pci config space without pciconfigall
Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
Remove pciconfigspace from pci devices, and py files
Add calcConfigAddr that returns address for config space based on bus/dev/function + offset

configs/test/fs.py:
    Update configuration for new default responder on bus
src/dev/ide_ctrl.cc:
src/dev/ide_ctrl.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
    Update to handle it's own pci config space without pciconfigall
src/dev/io_device.cc:
src/dev/io_device.hh:
    change naming for pio port
    break out recvTiming into two functions to reuse code
src/dev/pciconfigall.cc:
src/dev/pciconfigall.hh:
    removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
src/dev/pcireg.h:
    add a max size for PCI config space (per PCI spec)
src/dev/platform.cc:
src/dev/platform.hh:
    remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
    bus:dev:func and interrupt
src/dev/sinic.cc:
    remove pciconfigspace as it's no longer a needed parameter
src/dev/tsunami.cc:
src/dev/tsunami.hh:
src/dev/tsunami_pchip.cc:
src/dev/tsunami_pchip.hh:
    add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec)
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    add idea of default responder to bus
src/python/m5/objects/Pci.py:
    add config port for pci devices
    add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec)

--HG--
extra : convert_revision : 99db43b0a3a077f86611d6eaff6664a3885da7c9
2006-07-06 14:41:01 -04:00
Kevin Lim
05eef5ee15 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 00f8eecf99c771ae8943ed1d3a652bfbcfe1c6bc
2006-07-06 13:59:13 -04:00
Kevin Lim
30c516d51c Support for draining, and the new method of switching out. Now switching out happens after the pipeline has been drained, deferring the three way handshake to the normal drain mechanism. The calls of switchOut() and takeOverFrom() both take action immediately.
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
    Support for draining, new method of switching out.

--HG--
extra : convert_revision : 05bf8b271ec85b3e2c675c3bed6c42aeba21f465
2006-07-06 13:59:02 -04:00
Kevin Lim
8c547d80b1 Change the return value of drain. False means the object wasn't able to drain yet.
src/python/m5/config.py:
    Invert the return value.
src/sim/sim_object.cc:
    Invert the return value of drain.
src/sim/sim_object.hh:
    Change the return value of drain.

--HG--
extra : convert_revision : 41bb122c6f29302d8b3815d7bd6a2ea8fba64df9
2006-07-06 13:57:21 -04:00
Korey Sewell
e60f998e29 Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALPHA_ISA"... wierd but OK
--HG--
extra : convert_revision : f847d6c01212e32200a319c16596b8e1c1d15c7d
2006-07-06 12:29:34 -04:00
Korey Sewell
a35898c18d Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 2f08ea52ef54118d42aa590c0d86aa0cc7988713
2006-07-06 12:19:29 -04:00
Korey Sewell
03fa13b27c Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.
src/cpu/cpu_models.py:
    Use O3DynInst
src/cpu/o3/dyn_inst.hh:
    declare O3DynInst here based off of ISA ... this must be updated for each ISA.
src/cpu/static_inst.hh:
    take out O3 forward declarations here and include header file to keep this file clean

--HG--
extra : convert_revision : 0d65463479c3cfc2d1154935b1032dae32c5efd0
2006-07-06 12:18:55 -04:00
Korey Sewell
215041215b more steps toward O3 SMT
src/arch/mips/isa/formats/fp.isa:
    Adjust for newmem
src/cpu/cpu_models.py:
    Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
    take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
    open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
    Add O3DynInst
src/cpu/o3/dyn_inst.hh:
    Use to get ISA-specific O3DynInst

--HG--
extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
2006-07-06 11:25:44 -04:00
Kevin Lim
eceba1405a For now using the checkpoint or switchcpu pseudo instructions will return control to Python, returning the cause to be the instruction name. The user's script must then interpret the reason for exiting the simulation loop and handle the action accordingly. This may change in the future.
src/sim/pseudo_inst.cc:
    Exit sim loop with a specific string to indicate to Python what caused the exit.  The user's script needs to interpret the exit events and handle them as desired.

--HG--
extra : convert_revision : 8eb4a42285dacb3ada3a791173c605b5acb78598
2006-07-05 23:38:11 -04:00
Kevin Lim
d598061dd6 Remove sampler and serializer. Now they are handled through C++ interacting with Python.
src/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/sim/pseudo_inst.cc:
    Remove sampler.
src/sim/sim_object.cc:
    Remove serializer.

--HG--
extra : convert_revision : ce7616189440f3dc70040148da6d07309a386008
2006-07-05 21:14:36 -04:00
Kevin Lim
d8fd09cc15 Rename quiesce to drain to avoid confusion with the pseudo instruction.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/python/m5/__init__.py:
src/python/m5/config.py:
src/sim/main.cc:
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_object.cc:
src/sim/sim_object.hh:
    Rename quiesce to drain.

--HG--
extra : convert_revision : fc3244a3934812e1edb8050f1f51f30382baf774
2006-07-05 17:59:33 -04:00
Kevin Lim
bd26dbdb13 Checker ignores any faults that occur in syscall emulation mode for now.
src/cpu/checker/cpu_impl.hh:
    The only fault we handle in SE causes troubles when invoked with the Checker.  This is because it changes state within the process, and not the checker, so the state isn't correct when the main CPU calls invoke.  It's safe to just ignore the fault in the Checker and continue.

--HG--
extra : convert_revision : 5000d763a75009c7a6011646a6790ac5b23df6bb
2006-07-05 17:25:37 -04:00
Kevin Lim
ea9697250c Fix up some merge problems.
src/base/traceflags.py:
    Remove BaseCPU traceflag.
src/cpu/o3/alpha/params.hh:
    Move non-Alpha specific parameters out of this params class.
src/cpu/o3/params.hh:
    Move non-Alpha specific params into this params class.

--HG--
extra : convert_revision : e5b652adb47a240376733400e6054c66c50bd514
2006-07-05 16:54:24 -04:00
Kevin Lim
b973fae85d Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

src/base/traceflags.py:
src/cpu/SConscript:
    Hand merge.
src/cpu/o3/alpha/params.hh:
    Hand merge.  This needs to get changed.

--HG--
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a
2006-07-05 16:08:18 -04:00
Kevin Lim
ae78c46531 Need to change state upon quiescing.
--HG--
extra : convert_revision : 25e3b0a463a0191cab9290665409d0abca6a179a
2006-07-05 15:57:02 -04:00
Kevin Lim
e41fd9cb63 Alphabetize traceflags, rename FullCPUAll flag to O3CPUAll.
--HG--
extra : convert_revision : f558966154376223674c82d513afc2dad6591426
2006-07-05 15:55:45 -04:00
Kevin Lim
b0ed531bd8 Split off files that are shared across the O3 and Ozone models.
--HG--
extra : convert_revision : 023e84660d5cee5162d39548f87e5ca8ec68115f
2006-07-05 15:53:22 -04:00
Kevin Lim
b84103811d Add some different parameters. The main change is that the writeback count is now limited so that it doesn't overflow the buffer.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
    Add in dispatchWidth, wbWidth, wbDepth parameters.  wbDepth is the number of cycles of wbWidth instructions that can be buffered.
src/cpu/o3/iew.hh:
    Include separate parameter for dispatch width.
    Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed.  The IQ must make sure with the IEW stage that it can issue instructions prior to issuing.
src/cpu/o3/iew_impl.hh:
    Include separate parameter for dispatch width.
    Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed.
src/cpu/o3/inst_queue_impl.hh:
    IQ needs to check with the IEW to make sure it can issue instructions, and increments the IEW wb counter each time there is an outstanding instruction that will writeback.
src/cpu/o3/lsq_unit_impl.hh:
    Be sure to decrement the writeback counter if there's a squashed load that returned.
src/python/m5/objects/AlphaO3CPU.py:
    Change the parameters to include dispatch width, writeback width, and writeback depth.

--HG--
extra : convert_revision : 31c8cc495273e3c481b79055562fc40f71291fc4
2006-07-05 15:51:36 -04:00
Ron Dreslinski
4201ec84b2 Fix some unset values in the request in the timing CPU.
Properly implement the MSHR allocate function.

src/cpu/simple/timing.cc:
    Set the thread context in the CPU.

    Need to do this properly, currently I just set it to Cpu=0 Thread=0.  This will just cause all the stats in the cache based on these to just yield totals and not a distribution.
src/mem/cache/miss/mshr.cc:
    Properly implement the allocate function for the MSHR.

--HG--
extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e
2006-07-05 15:13:27 -04:00
Korey Sewell
f4c5609988 Fix for FS O3CPU compile ... missing forward class declaration/header file after files got split for ISA-independence
src/cpu/o3/alpha/thread_context.hh:
    Use 'this' when accessing cpu
src/cpu/o3/cpu.hh:
    add numActiveThreds function
src/cpu/o3/thread_context.hh:
    forward class declarations
src/cpu/o3/thread_context_impl.hh:
    add quiesce event header file
src/cpu/thread_context.hh:
    add exit() function to thread context (read comments in file)
src/sim/syscall_emul.cc:
    adjust exitFunc syscall

--HG--
extra : convert_revision : 323dc871e2b4f4ee5036be388ceb6634cd85a83e
2006-07-03 12:19:35 -04:00
Korey Sewell
19083bc4ce Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
the workloads.

Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" -i="file1;file2"

I think I am a novice python magician now!!!!....

configs/test/test.py:
    Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
    the workloads.

    Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" --input="file1;file2"
    (btw, We are back to working for this double hello world case)

    I am a novice python magician now!!!!....

--HG--
extra : convert_revision : b55e10dce33f5a9dc4c78f90409ec0912bad4292
2006-07-03 01:10:19 -04:00
Korey Sewell
cf58578ba1 typo ... change 'single_thread' to 'round_robin_policy'
--HG--
extra : convert_revision : a4a5cb90557f786d42c6178bc6e268312c5ecbee
2006-07-02 23:27:13 -04:00
Korey Sewell
c8b3d8a1ed Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)
Edit Test3 for newmem

src/base/traceflags.py:
    Add O3CPU flag
src/cpu/base.cc:
    for some reason adding a BaseCPU flag doesnt work so just go back to old way...
src/cpu/o3/alpha/cpu_builder.cc:
    Determine number threads by workload size instead of solely by parameter.

    Default SMT fetch policy to RoundRobin if it's not specified in Config file
src/cpu/o3/commit.hh:
    only use nextNPC for !ALPHA
src/cpu/o3/commit_impl.hh:
    add FetchTrapPending as condition for commit
src/cpu/o3/cpu.cc:
    panic if active threads is more than Impl::MaxThreads
src/cpu/o3/fetch.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
    name stuff
src/cpu/o3/fetch_impl.hh:
    fatal if try to use SMT branch count, that's unimplemented right now
src/python/m5/config.py:
    make it clearer that a parameter is not valid within a configuration class

--HG--
extra : convert_revision : 55069847304e40e257f9225f0dc3894ce6491b34
2006-07-02 23:11:24 -04:00
Korey Sewell
23cfd9489b traceflag stuff
src/base/traceflags.py:
    add BaseCPU flag, O3CPUAll flag grouping
src/cpu/base.cc:
    Use BaseCPU flag instead of FullCPU flag

--HG--
extra : convert_revision : 32f737a2f58eb936634799f1f809e07cbba90179
2006-07-01 19:02:43 -04:00
Korey Sewell
62961a2916 fix cpu builder to build the correct name...
add activateThread event and functions

src/cpu/o3/alpha/cpu_builder.cc:
    Have CPU builder build a DerivO3CPU not a DerivAlphaO3CPU
src/cpu/o3/cpu.cc:
    add activateThread Event

    add activateThread function

    adjust activateContext to schedule a thread to activate within the
    CPU instead of activating thread right away. This will lead to stages
    trying to use threads that  arent ready yet and wasting execution time & possibly
    performance.
src/cpu/o3/cpu.hh:
    add activateThread Event

    add activateThread function

    add schedule/descheculed activate thread event

--HG--
extra : convert_revision : 236d30dc160910507ad36f7f527ab185ed38dc04
2006-07-01 18:52:02 -04:00
Korey Sewell
ed821702e0 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 3c1405d8b4831c6240e02ba65a72043ca55f4a46
2006-06-30 20:51:07 -04:00
Korey Sewell
51261196bd now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
src/cpu/o3/alpha/cpu.cc:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/impl.hh:
    filenames
src/cpu/o3/alpha/thread_context.hh:
    public
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use O3CPUImpl ... not Alpha
src/cpu/o3/checker_builder.cc:
    filename

--HG--
extra : convert_revision : 6eb739909699ade1e2a9d63637b182413ceebc69
2006-06-30 20:49:31 -04:00
Korey Sewell
d9ef772e8d Make O3CPU model independent of the ISA
Use O3CPU when building instead of AlphaO3CPU.

I could use some better python magic in the cpu_models.py file!

AUTHORS:
    add middle initial
SConstruct:
    change from AlphaO3CPU to O3CPU
src/cpu/SConscript:
    edits to build O3CPU instead of AlphaO3CPU
src/cpu/cpu_models.py:
    change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model...

    Actually, some Python expertise could be used here. The 'env' variable is not
    passed to this file, so I had to parse through the ARGV to find the ISA...
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use isa_specific.hh
src/sim/process.cc:
    only initi NextNPC if not ALPHA
src/cpu/o3/alpha/cpu.cc:
    alphao3cpu impl
src/cpu/o3/alpha/cpu.hh:
    move AlphaTC to it's own file
src/cpu/o3/alpha/cpu_impl.hh:
    Move AlphaTC to it's own file ...
src/cpu/o3/alpha/dyn_inst.cc:
src/cpu/o3/alpha/dyn_inst.hh:
src/cpu/o3/alpha/dyn_inst_impl.hh:
    include paths
src/cpu/o3/alpha/impl.hh:
    include paths, set default MaxThreads to 2 instead of 4
src/cpu/o3/alpha/params.hh:
    set Alpha Specific Params here
src/python/m5/objects/O3CPU.py:
    add O3CPU class
src/cpu/o3/SConscript:
    include isa-specific build files
src/cpu/o3/alpha/thread_context.cc:
    NEW HOME of AlphaTC
src/cpu/o3/alpha/thread_context.hh:
    new home of AlphaTC
src/cpu/o3/isa_specific.hh:
    includes ISA specific files
src/cpu/o3/params.hh:
    base o3 params
src/cpu/o3/thread_context.hh:
    base o3 thread context
src/cpu/o3/thread_context_impl.hh:
    base o3 thead context impl

--HG--
rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc
rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh
rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc
rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh
rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh
rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e
2006-06-30 19:52:08 -04:00
Ron Dreslinski
7a49298134 AtomicSimpleCPU with a cache now runs the hello world! test program.
Need to clean up a bunch of flags/hacks in the code.  Then onto Timming mode.

Functional accesses also work properly, although not exactly how we wanted them.  I'll need to clean that up as well.

src/cpu/simple/atomic.cc:
    Atomic CPU needs to set thread context so stats work in cache.  Temporarily just use CPU=0 ThreadID=0
src/mem/cache/cache_impl.hh:
    Need to return success/failure properly still
    Physical memory object doesn't assert SATISFIED anymore, need to remove that flag
src/mem/cache/tags/lru.cc:
    Doesn't work if the REQ doesn't set it's ASID.  Temporary fix use 0 always

--HG--
extra : convert_revision : d06a39684af593db699b64df9a29f80c61d8d050
2006-06-30 17:21:58 -04:00
Ron Dreslinski
1bdc65b00f First pass, now compiles with current head of tree.
Compile and initialization work, still working on functionality.

src/mem/cache/base_cache.cc:
    Temp fix for cpu's use of getPort functionality.  CPU's will need to be ported to the new connector objects.
    Also, all packets have to have data or the delete fails.
src/mem/cache/cache.hh:
    Fix function prototypes so overloading works
src/mem/cache/cache_impl.hh:
    fix functions to match virtual base class
src/mem/cache/miss/miss_queue.cc:
    Packets havve to have data, or delete fails
src/python/m5/objects/BaseCache.py:
    Update for newmem

--HG--
extra : convert_revision : 2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb
2006-06-30 16:25:35 -04:00
Ron Dreslinski
dea1a19b2d Fix the packet data allocation methods. Small fixes from changesets after my initial work.
This now compiles.

src/mem/cache/base_cache.cc:
    Fix getPort function that changed
src/mem/cache/base_cache.hh:
    Fix get port function, provide default implementations of virtual functions in the base class
src/mem/cache/cache.hh:
    Fix virtual function declerations
src/mem/cache/cache_builder.cc:
    Fix params
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
    Properly allocate data in packet

--HG--
extra : convert_revision : dedf8b0f76ab90b06b60f8fe079c0ae361f91a48
2006-06-30 11:34:27 -04:00
Ron Dreslinski
971bb55369 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 6eefb4a3ee472f2f2c86ed823c70fc9e5625818f
2006-06-30 10:25:50 -04:00
Ron Dreslinski
335fa4bde3 All files compile in the mem directory except cache_builder
Missing some functionality (like split caches and copy support)

src/SConscript:
    Typo
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/ghb_prefetcher.hh:
src/mem/cache/prefetch/stride_prefetcher.hh:
src/mem/cache/prefetch/tagged_prefetcher_impl.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.hh:
src/mem/request.hh:
    Fix so it compiles

--HG--
extra : convert_revision : 0d87d84f6e9445bab655c0cb0f8541bbf6eab904
2006-06-30 10:25:25 -04:00
Kevin Lim
0fbecab797 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0756f7f1f63fae472e0ef1d20e9eb38e56de78c8
2006-06-29 21:38:16 -04:00
Kevin Lim
ad6788493c Remove function that no longer can be used. We should figure out if we want to allow the m5checkpoint pseudoinstruction or not.
src/sim/pseudo_inst.cc:
    Remove the setup function from Checkpoint.  I'm not sure what we want to do with this pseudoinst.
src/sim/serialize.hh:
    Remove setup function.

--HG--
extra : convert_revision : 5ff494d816e2d8a7fe65a3d13037608003388d8f
2006-06-29 21:34:01 -04:00
Kevin Lim
2416ba606a Various fixes for the CPU models to support the features that have been moved to python.
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/simple/atomic.hh:
    Switching out no longer takes a sampler.
src/cpu/simple/atomic.cc:
    Fix up switching out.  Also fix up serialization; the nameOut() was messing up the ordering.
src/cpu/simple/timing.cc:
    Add in quiesce, fix up serialization.
src/cpu/simple/timing.hh:
    Add in queisce, fix up serialization.

--HG--
extra : convert_revision : 9d59d53bdf269d4d82fb119e5ae7c8a5d475880b
2006-06-29 19:45:24 -04:00
Kevin Lim
f64c175f9a Add in support for quiescing the system, taking checkpoints, restoring from checkpoints, changing memory modes, and switching CPUs.
Key new functions that can be called on the m5 object at the python interpreter:
doQuiesce(root) - A helper function that quiesces the object passed in and all of its children.
resume(root) - Another helper function that tells the object and all of its children that the quiesce is over.
checkpoint(root) - Takes a checkpoint of the system.  Checkpoint directory must be set before hand.
setCheckpointDir(name) - Sets the checkpoint directory.
restoreCheckpoint(root) - Restores the values from the checkpoint located in the checkpoint directory.
changeToAtomic(system) - Changes the system and all of its children to atomic memory mode.
changeToTiming(system) - Changes the system and all of its children to timing memory mode.
switchCpus(list) - Takes in a list of tuples, where each tuple is a pair of (old CPU, new CPU).  Quiesces the old CPUs, and then switches over to the new CPUs.

src/SConscript:
    Remove serializer, replaced by python code.
src/python/m5/__init__.py:
    Updates to support quiescing, checkpointing, changing memory modes, and switching CPUs.
src/python/m5/config.py:
    Several functions defined on the SimObject for quiescing, changing timing modes, and switching CPUs
src/sim/main.cc:
    Add some extra functions that are exported to python through SWIG.
src/sim/serialize.cc:
    Change serialization around a bit.  Now it is controlled through Python, so there's no need for SerializeEvents or SerializeParams.

    Also add in a new unserializeAll() function that loads a checkpoint and handles unserializing all objects.
src/sim/serialize.hh:
    Add unserializeAll function and a setCheckpointName function.
src/sim/sim_events.cc:
    Add process() function for CountedQuiesceEvent, which calls exitSimLoop() once its counter reaches 0.
src/sim/sim_events.hh:
    Add in a CountedQuiesceEvent, which is used when the system is preparing to quiesce.  Any objects that can't be quiesced immediately are given a pointer to a CountedQuiesceEvent.  The event has its counter set via Python, and as objects finish quiescing they call process() on the event.  Eventually the event causes the simulation to stop once all objects have quiesced.
src/sim/sim_object.cc:
    Add a few functions for quiescing, checkpointing, and changing memory modes.
src/sim/sim_object.hh:
    Add a state variable to all SimObjects that tracks both the timing mode of the object and the quiesce state of the object.  Currently this isn't serialized, and I'm not sure it needs to be so long as the timing mode starts up the same after a checkpoint.

--HG--
extra : convert_revision : a8c738d3911c68d5a7caf7de24d732dcc62cfb61
2006-06-29 19:40:12 -04:00