Fix the packet data allocation methods. Small fixes from changesets after my initial work.

This now compiles.

src/mem/cache/base_cache.cc:
    Fix getPort function that changed
src/mem/cache/base_cache.hh:
    Fix get port function, provide default implementations of virtual functions in the base class
src/mem/cache/cache.hh:
    Fix virtual function declerations
src/mem/cache/cache_builder.cc:
    Fix params
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
    Properly allocate data in packet

--HG--
extra : convert_revision : dedf8b0f76ab90b06b60f8fe079c0ae361f91a48

src/mem/cache/base_cache.cc

@@ -99,7 +99,7 @@ BaseCache::CachePort::clearBlocked()
 }
 
 Port*
-BaseCache::getPort(const std::string &if_name)
+BaseCache::getPort(const std::string &if_name, int idx)
 {
     if(if_name == "cpu_side")
     {

src/mem/cache/base_cache.hh

@@ -41,6 +41,7 @@
 #include <list>
 #include <inttypes.h>
 
+#include "base/misc.hh"
 #include "base/statistics.hh"
 #include "base/trace.hh"
 #include "mem/mem_object.hh"
@@ -122,14 +123,29 @@ class BaseCache : public MemObject
     CachePort *memSidePort;
 
   public:
-    virtual Port *getPort(const std::string &if_name);
+    virtual Port *getPort(const std::string &if_name, int idx = -1);
 
   private:
     //To be defined in cache_impl.hh not in base class
-    virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide);
-    virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
-    virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
-    virtual void recvStatusChange(Port::Status status, bool isCpuSide);
+    virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+    {
+        fatal("No implementation");
+    }
+
+    virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
+    {
+        fatal("No implementation");
+    }
+
+    virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
+    {
+        fatal("No implementation");
+    }
+
+    virtual void recvStatusChange(Port::Status status, bool isCpuSide)
+    {
+        fatal("No implementation");
+    }
 
     /**
      * Bit vector of the blocking reasons for the access path.

src/mem/cache/cache.hh

@@ -146,16 +146,16 @@ class Cache : public BaseCache
     /** Instantiates a basic cache object. */
     Cache(const std::string &_name, Params &params);
 
-    bool doTimingAccess(Packet *pkt, CachePort *cachePort,
+    virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
                         bool isCpuSide);
 
-    Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
+    virtual Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
                         bool isCpuSide);
 
-    void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
+    virtual void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
                             bool isCpuSide);
 
-    void recvStatusChange(Port::Status status, bool isCpuSide);
+    virtual void recvStatusChange(Port::Status status, bool isCpuSide);
 
     void regStats();
 

src/mem/cache/cache_builder.cc

@@ -230,7 +230,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
         Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
                                                        do_copy, base_params, \
                                                        /*in_bus, out_bus,*/ pf,  \
-                                                       prefetch_access); \
+                                                       prefetch_access, hit_latency); \
         Cache<CacheTags<t, comp>, b, c> *retval =			\
             new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
                                                 params);		\
@@ -242,7 +242,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
         retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
         out_bus->rangeChange();						\
         return retval;							\
-*/return true;                                                          \
+*/return retval;                                                          \
     } while (0)
 
 #define BUILD_CACHE_PANIC(x) do {			\

src/mem/cache/cache_impl.hh

@@ -588,8 +588,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
 
                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 
-                uint8_t* temp_data = new uint8_t[blkSize];
-                busPkt->dataDynamicArray<uint8_t>(temp_data);
+                busPkt->allocate();
 
                 busPkt->time = curTick;
 

src/mem/cache/miss/blocking_buffer.cc

@@ -210,8 +210,7 @@ BlockingBuffer::doWriteback(Addr addr, int asid,
     // Generate request
     Request * req = new Request(addr, size, 0);
     Packet * pkt = new Packet(req, Packet::Writeback, -1);
-    uint8_t *new_data = new uint8_t[size];
-    pkt->dataDynamicArray<uint8_t>(new_data);
+    pkt->allocate();
     if (data) {
         memcpy(pkt->getPtr<uint8_t>(), data, size);
     }

src/mem/cache/miss/miss_queue.cc

@@ -714,8 +714,7 @@ MissQueue::doWriteback(Addr addr, int asid,
     // Generate request
     Request * req = new Request(addr, size, 0);
     Packet * pkt = new Packet(req, Packet::Writeback, -1);
-    uint8_t *new_data = new uint8_t[size];
-    pkt->dataDynamicArray<uint8_t>(new_data);
+    pkt->allocate();
     if (data) {
         memcpy(pkt->getPtr<uint8_t>(), data, size);
     }

src/mem/cache/miss/mshr.cc

@@ -90,8 +90,7 @@ MSHR::allocateAsBuffer(Packet * &target)
     asid = target->req->getAsid();
     threadNum = target->req->getThreadNum();
     pkt = new Packet(target->req, target->cmd, -1);
-    uint8_t *new_data = new uint8_t[target->getSize()];
-    pkt->dataDynamicArray<uint8_t>(new_data);
+    pkt->allocate();
     pkt->senderState = (Packet::SenderState*)this;
     pkt->time = curTick;
 }

src/mem/cache/prefetch/base_prefetcher.cc

@@ -181,8 +181,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
             Request * prefetchReq = new Request(*addr, blkSize, 0);
             Packet * prefetch;
             prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1);
-            uint8_t *new_data = new uint8_t[blkSize];
-            prefetch->dataDynamicArray<uint8_t>(new_data);
+            prefetch->allocate();
             prefetch->req->setThreadContext(pkt->req->getCpuNum(),
                                             pkt->req->getThreadNum());
 

src/mem/cache/tags/iic.cc

@@ -430,10 +430,11 @@ IIC::freeReplacementBlock(PacketList & writebacks)
                                   tag_ptr->data,
                                   tag_ptr->size);
 */
-        Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
+            Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
                                            blkSize, 0);
-        Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
-        writeback->dataDynamic<uint8_t>(tag_ptr->data);
+            Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
+            writeback->allocate();
+            memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize);
 
             writebacks.push_back(writeback);
         }

src/mem/cache/tags/lru.cc

@@ -280,7 +280,8 @@ LRU::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks)
                                                                   dest_blk->set),
                                                 blkSize, 0);
             Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
-            writeback->dataDynamic<uint8_t>(dest_blk->data);
+            writeback->allocate();
+            memcpy(writeback->getPtr<uint8_t>(),dest_blk->data, blkSize);
             writebacks.push_back(writeback);
         }
         dest_blk->tag = extractTag(dest);