2006-10-12 21:04:14 +02:00
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---------- Begin Simulation Statistics ----------
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2011-04-22 19:18:51 +02:00
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host_inst_rate 170645 # Simulator instruction rate (inst/s)
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host_mem_usage 211856 # Number of bytes of host memory used
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host_seconds 493.30 # Real time elapsed on the host
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host_tick_rate 69310511 # Simulator tick rate (ticks/s)
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2006-10-12 21:04:14 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2007-02-27 11:37:48 +01:00
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sim_insts 84179709 # Number of instructions simulated
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2011-04-04 18:42:25 +02:00
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sim_seconds 0.034191 # Number of seconds simulated
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sim_ticks 34191076000 # Number of ticks simulated
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-04-04 18:42:25 +02:00
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system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target.
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system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.branches 10240685 # Number of branches committed
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system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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2007-02-27 11:37:48 +01:00
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system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
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2007-02-17 10:38:13 +01:00
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system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
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2011-04-04 18:42:25 +02:00
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system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle
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system.cpu.commit.count 91903055 # Number of instructions committed
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system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 1029620 # Number of function calls committed.
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system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
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system.cpu.commit.loads 19996198 # Number of loads committed
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system.cpu.commit.membars 0 # Number of memory barriers committed
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system.cpu.commit.refs 26497301 # Number of memory references committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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2007-02-27 11:37:48 +01:00
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system.cpu.committedInsts 84179709 # Number of Instructions Simulated
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system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
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2011-04-04 18:42:25 +02:00
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system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles
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2007-08-27 05:27:53 +02:00
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses
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2008-03-18 04:07:22 +01:00
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system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks.
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context
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2011-04-20 03:45:23 +02:00
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system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_hits 30012251 # number of overall hits
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system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_misses 8940 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.replacements 160 # number of replacements
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2010-11-08 20:58:24 +01:00
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system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use
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system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.writebacks 109 # number of writebacks
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2011-04-20 03:45:23 +02:00
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system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked
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system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction
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system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch
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system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode
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system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle
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system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running
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system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing
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system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode
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system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking
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2011-04-04 18:42:25 +02:00
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system.cpu.dtb.data_accesses 32239873 # DTB accesses
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.data_acv 0 # DTB access violations
|
2011-04-04 18:42:25 +02:00
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system.cpu.dtb.data_hits 31883201 # DTB hits
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system.cpu.dtb.data_misses 356672 # DTB misses
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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|
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system.cpu.dtb.fetch_hits 0 # ITB hits
|
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system.cpu.dtb.fetch_misses 0 # ITB misses
|
2011-04-04 18:42:25 +02:00
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|
|
system.cpu.dtb.read_accesses 24961741 # DTB read accesses
|
2007-08-27 05:27:53 +02:00
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|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.read_hits 24606273 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 355468 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_accesses 7278132 # DTB write accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.write_hits 7276928 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 1204 # DTB write misses
|
|
|
|
|
system.cpu.fetch.Branches 17634633 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 27321847 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.SquashCycles 2202221 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.fetch.rateDist::samples 68273622 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.184313 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.130987 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.fetch.rateDist::0 40951775 59.98% 59.98% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 2771290 4.06% 64.04% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 1819003 2.66% 66.71% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 3013999 4.41% 71.12% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 3778689 5.53% 76.65% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 1379239 2.02% 78.67% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 1617985 2.37% 81.04% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 1572355 2.30% 83.35% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 11369287 16.65% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.fetch.rateDist::total 68273622 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_hits 17386201 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 11068 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.replacements 8218 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.exec_branches 12448390 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_nop 11194543 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.455255 # Inst execution rate
|
|
|
|
|
system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_stores 7278167 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking
|
2011-04-22 19:18:51 +02:00
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 1076434 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 361752 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 9740 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 8840023 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 2710213 # Number of stores squashed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_producers 64595544 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.int_regfile_reads 134796814 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 73485618 # number of integer regfile writes
|
|
|
|
|
system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 138886536 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.rate 1.490981 # Inst issue rate
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.itb.fetch_accesses 17397343 # ITB accesses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.itb.fetch_hits 17397269 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 74 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 1709 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 116176000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks.
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 159115500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.411893 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.overall_hits 7279 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 5098 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.misc_regfile_reads 712206 # number of misc regfile reads
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.numCycles 68382153 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.serializingInsts 469 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.rob.rob_reads 186605606 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 260771760 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.workload.num_syscalls 389 # Number of system calls
|
2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
