2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-08-13 01:43:55 +02:00
|
|
|
global.BPredUnit.BTBHits 13022932 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 16938031 # Number of BTB lookups
|
|
|
|
|
global.BPredUnit.RASInCorrect 1193 # Number of incorrect RAS predictions.
|
|
|
|
|
global.BPredUnit.condIncorrect 1944645 # Number of conditional branches incorrect
|
|
|
|
|
global.BPredUnit.condPredicted 14588431 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 19441115 # Number of BP lookups
|
|
|
|
|
global.BPredUnit.usedRAS 1715741 # Number of times the RAS was used to get a target.
|
|
|
|
|
host_inst_rate 140839 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 205524 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 597.70 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 68085854 # Simulator tick rate (ticks/s)
|
|
|
|
|
memdepunit.memDep.conflictingLoads 17320747 # Number of conflicting loads.
|
|
|
|
|
memdepunit.memDep.conflictingStores 5158870 # Number of conflicting stores.
|
|
|
|
|
memdepunit.memDep.insertedLoads 33916617 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
memdepunit.memDep.insertedStores 10592327 # Number of stores inserted to the mem dependence unit.
|
2006-10-12 21:04:14 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2007-02-27 11:37:48 +01:00
|
|
|
sim_insts 84179709 # Number of instructions simulated
|
2007-08-13 01:43:55 +02:00
|
|
|
sim_seconds 0.040695 # Number of seconds simulated
|
|
|
|
|
sim_ticks 40694900000 # Number of ticks simulated
|
2007-02-27 11:37:48 +01:00
|
|
|
system.cpu.commit.COM:branches 10240685 # Number of branches committed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 2814383 # number cycles where commit BW limit reached
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 73372540
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-08-13 01:43:55 +02:00
|
|
|
0 36054158 4913.85%
|
|
|
|
|
1 18224800 2483.87%
|
|
|
|
|
2 7501822 1022.43%
|
|
|
|
|
3 3901009 531.67%
|
|
|
|
|
4 2128189 290.05%
|
|
|
|
|
5 1274528 173.71%
|
|
|
|
|
6 744433 101.46%
|
|
|
|
|
7 729218 99.39%
|
|
|
|
|
8 2814383 383.57%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
2007-02-27 11:37:48 +01:00
|
|
|
system.cpu.commit.COM:count 91903055 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 20034413 # Number of loads committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
2007-02-27 11:37:48 +01:00
|
|
|
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.commit.branchMispredicts 1932230 # The number of times a branch was mispredicted
|
2007-02-27 11:37:48 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
|
2007-02-17 10:38:13 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 55717434 # The number of squashed insts skipped by commit
|
2007-02-27 11:37:48 +01:00
|
|
|
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.cpi 0.966851 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.966851 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 23356209 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 9066 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5569 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 23355709 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 4533000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000021 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 500 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2784500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 500 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 6495002 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 24564.959569 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5850.134771 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 6493147 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 45568000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1855 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 6101 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 10852000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1855 # number of WriteReq MSHR misses
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.avg_refs 13325.436607 # Average number of references to valid blocks.
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.demand_accesses 29851211 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 21274.309979 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 29848856 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 50101000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 2355 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 6224 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 13636500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 2355 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.overall_accesses 29851211 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 21274.309979 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.overall_hits 29848856 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 50101000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 2355 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 6224 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 13636500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 2355 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.replacements 160 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.tagsinuse 1458.130010 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 29848978 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.writebacks 106 # number of writebacks
|
|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 3820626 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 12575 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 3037417 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 162462210 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 39463165 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 29936850 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 8016661 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 44953 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 151900 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.fetch.Branches 19441115 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 19217268 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 50163624 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 510483 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 167309935 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 2078673 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.238866 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 19217268 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 14738673 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 2.055677 # Number of inst fetches per cycle
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 81389202
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-08-13 01:43:55 +02:00
|
|
|
0 50442849 6197.73%
|
|
|
|
|
1 3127409 384.25%
|
|
|
|
|
2 2013333 247.37%
|
|
|
|
|
3 3501649 430.24%
|
|
|
|
|
4 4585592 563.42%
|
|
|
|
|
5 1499931 184.29%
|
|
|
|
|
6 2042041 250.90%
|
|
|
|
|
7 1854540 227.86%
|
|
|
|
|
8 12321858 1513.94%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 19216915 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 5291.898608 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3156.958250 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 19206855 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 53236500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000523 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 10060 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 353 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 31759000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 10060 # number of ReadReq MSHR misses
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.avg_refs 1909.230119 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.demand_accesses 19216915 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 5291.898608 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 19206855 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 53236500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000523 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 10060 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 353 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 31759000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 10060 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.overall_accesses 19216915 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 5291.898608 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.overall_hits 19206855 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 53236500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000523 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 10060 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 353 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 31759000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 10060 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.replacements 8146 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 10060 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.tagsinuse 1551.624399 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 19206855 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.idleCycles 435727 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 12761226 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 12552336 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.247935 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 31899012 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 7188094 # Number of stores executed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.WB:consumers 90808493 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 99646578 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.722903 # average fanout of values written-back
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.WB:producers 65645732 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.224322 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 100573545 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 2105709 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 285403 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 33916617 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 1714541 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 10592327 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 147619094 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 24710918 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 2203361 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 101568426 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 132795 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 8016661 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 165683 # Number of cycles IEW is unblocking
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 838013 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 1487 # Number of memory responses ignored because the instruction is squashed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 249026 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 13882204 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 4089632 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 249026 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 202527 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1903182 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 1.034286 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.034286 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 103771787 # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2007-08-13 01:43:55 +02:00
|
|
|
No_OpClass 7 0.00% # Type of FU issued
|
|
|
|
|
IntAlu 64228940 61.89% # Type of FU issued
|
|
|
|
|
IntMult 473017 0.46% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
2007-08-13 01:43:55 +02:00
|
|
|
FloatAdd 2790055 2.69% # Type of FU issued
|
|
|
|
|
FloatCmp 115633 0.11% # Type of FU issued
|
|
|
|
|
FloatCvt 2376207 2.29% # Type of FU issued
|
|
|
|
|
FloatMult 305676 0.29% # Type of FU issued
|
|
|
|
|
FloatDiv 755062 0.73% # Type of FU issued
|
|
|
|
|
FloatSqrt 323 0.00% # Type of FU issued
|
|
|
|
|
MemRead 25409003 24.49% # Type of FU issued
|
|
|
|
|
MemWrite 7317864 7.05% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 1978136 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.019062 # FU busy rate (busy events/executed inst)
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
2007-08-13 01:43:55 +02:00
|
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntAlu 311313 15.74% # attempts to use FU when none available
|
2007-04-16 04:29:37 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
2007-08-13 01:43:55 +02:00
|
|
|
FloatAdd 546 0.03% # attempts to use FU when none available
|
2007-05-16 01:25:35 +02:00
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
2007-08-13 01:43:55 +02:00
|
|
|
FloatCvt 3483 0.18% # attempts to use FU when none available
|
|
|
|
|
FloatMult 2460 0.12% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 833660 42.14% # attempts to use FU when none available
|
2007-04-16 04:29:37 +02:00
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2007-08-13 01:43:55 +02:00
|
|
|
MemRead 753551 38.09% # attempts to use FU when none available
|
|
|
|
|
MemWrite 73123 3.70% # attempts to use FU when none available
|
2007-04-16 04:29:37 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 81389202
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-08-13 01:43:55 +02:00
|
|
|
0 35308856 4338.27%
|
|
|
|
|
1 18677963 2294.89%
|
|
|
|
|
2 11652538 1431.71%
|
|
|
|
|
3 6999702 860.03%
|
|
|
|
|
4 4887440 600.50%
|
|
|
|
|
5 2229546 273.94%
|
|
|
|
|
6 1377818 169.29%
|
|
|
|
|
7 217468 26.72%
|
|
|
|
|
8 37871 4.65%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 1.275007 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 135066329 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 103771787 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 50270340 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 231965 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 47066497 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1741 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 4485.353245 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2485.353245 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 7809000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 1741 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4327000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1741 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 10559 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4274.193548 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2274.193548 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 7149 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 14575000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.322947 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 3410 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 7755000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.322947 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 3410 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 118 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4500 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2500 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 531000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 118 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 295000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 118 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_misses 106 # number of Writeback misses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_misses 106 # number of Writeback MSHR misses
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.avg_refs 2.172948 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 12300 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 4345.563968 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 7149 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 22384000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.418780 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 5151 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 12082000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.418780 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 5151 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 12300 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 4345.563968 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.overall_hits 7149 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 22384000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.418780 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 5151 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 12082000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.418780 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 5151 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 3290 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 2252.890734 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 7149 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.numCycles 81389202 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 1683934 # Number of cycles rename is blocking
|
2007-02-27 11:37:48 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 1032549 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 40751116 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 970163 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 202965992 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 157380306 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 115963922 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 28805465 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 8016661 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 2127274 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 47536561 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 4752 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 464 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 4689522 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 453 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 283 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2007-02-17 10:38:13 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
