gem5/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout

M5 Simulator System

Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved


M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 02:44:06
M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0.  Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 7183000 because target called exit()
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1 2006-09-01 23:59:36 +02:00			`M5 Simulator System`

Bus: Update the stats for the recent bus fix. --HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407 2008-02-26 08:20:40 +01:00			`Copyright (c) 2001-2008`
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1 2006-09-01 23:59:36 +02:00			`The Regents of The University of Michigan`
			`All Rights Reserved`


stats: update stats for the changes I pushed re: shared cache occupancy 2010-02-25 19:08:41 +01:00			`M5 compiled Feb 24 2010 23:12:40`
			`M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip`
			`M5 started Feb 25 2010 02:44:06`
			`M5 executing on SC2B0619`
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests. 2009-04-22 07:55:52 +02:00			`command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing`
Update stats for changes. --HG-- extra : convert_revision : a24c4cd7e2fcd732f5da5679f0c0fbf205f22815 2007-03-25 07:05:48 +02:00			`Global frequency set at 1000000000000 ticks per second`
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache. 2008-11-06 17:11:42 +01:00			`info: Entering event queue @ 0. Starting simulation...`
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway. 2009-02-16 18:09:45 +01:00			`info: Increasing stack size by one page.`
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion. 2008-07-22 23:00:18 +02:00			`Hello world!`
Make default PhysicalMemory latency slightly more realistic. Also update stats to reflect change. 2008-08-04 00:13:29 +02:00			`Exiting @ tick 7183000 because target called exit()`