gem5/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt

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---------- Begin Simulation Statistics ----------
Update Alpha reference stats for clock changes. tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out: tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out: tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out: tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr: Update refs for clock changes. --HG-- extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42
2007-04-27 20:35:58 +02:00
sim_seconds 0.199332 # Number of seconds simulated
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3310187 # Simulator instruction rate (inst/s)
host_op_rate 3310187 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1655094150 # Simulator tick rate (ticks/s)
host_mem_usage 226700 # Number of bytes of host memory used
host_seconds 120.44 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory
system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory
system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory
system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory
system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 13793364824 # Throughput (bytes/s)
system.membus.data_through_bus 2749464673 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754489 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754510 # DTB read accesses
system.cpu.dtb.write_hits 73520729 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73520764 # DTB write accesses
system.cpu.dtb.data_hits 168275218 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275274 # DTB accesses
system.cpu.itb.fetch_hits 398664651 # ITB hits
system.cpu.itb.fetch_misses 173 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 398664824 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 398664824 # number of cpu cycles simulated
2011-02-08 04:23:13 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 398664595 # Number of instructions committed
system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed
2011-02-08 04:23:13 +01:00
system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
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system.cpu.num_int_insts 316365907 # number of integer instructions
system.cpu.num_fp_insts 155295119 # number of float instructions
2011-02-08 04:23:13 +01:00
system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
2011-02-08 04:23:13 +01:00
system.cpu.num_mem_refs 168275274 # number of memory refs
system.cpu.num_load_insts 94754510 # Number of load instructions
2011-02-08 04:23:13 +01:00
system.cpu.num_store_insts 73520764 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 398664824 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------