2006-05-16 23:36:50 +02:00
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/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Steve Reinhardt
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2006-05-16 23:36:50 +02:00
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*/
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#ifndef __CPU_SIMPLE_TIMING_HH__
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#define __CPU_SIMPLE_TIMING_HH__
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#include "cpu/simple/base.hh"
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2010-02-12 20:53:19 +01:00
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#include "cpu/translation.hh"
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2008-08-11 21:22:16 +02:00
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#include "params/TimingSimpleCPU.hh"
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2006-05-16 23:36:50 +02:00
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class TimingSimpleCPU : public BaseSimpleCPU
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{
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public:
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2008-08-11 21:22:16 +02:00
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TimingSimpleCPU(TimingSimpleCPUParams * params);
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2006-05-16 23:36:50 +02:00
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virtual ~TimingSimpleCPU();
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virtual void init();
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public:
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2006-07-05 23:59:33 +02:00
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Event *drainEvent;
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2006-06-30 01:45:24 +02:00
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2006-05-16 23:36:50 +02:00
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private:
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2008-11-10 06:56:28 +01:00
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/*
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* If an access needs to be broken into fragments, currently at most two,
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* the the following two classes are used as the sender state of the
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* packets so the CPU can keep track of everything. In the main packet
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* sender state, there's an array with a spot for each fragment. If a
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* fragment has already been accepted by the CPU, aka isn't waiting for
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* a retry, it's pointer is NULL. After each fragment has successfully
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* been processed, the "outstanding" counter is decremented. Once the
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* count is zero, the entire larger access is complete.
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*/
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class SplitMainSenderState : public Packet::SenderState
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{
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public:
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int outstanding;
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PacketPtr fragments[2];
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int
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getPendingFragment()
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{
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if (fragments[0]) {
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return 0;
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} else if (fragments[1]) {
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return 1;
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} else {
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return -1;
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}
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}
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};
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class SplitFragmentSenderState : public Packet::SenderState
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{
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public:
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SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
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bigPkt(_bigPkt), index(_index)
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{}
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PacketPtr bigPkt;
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int index;
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void
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clearFromParent()
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{
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SplitMainSenderState * main_send_state =
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dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
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main_send_state->fragments[index] = NULL;
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}
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};
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2009-02-25 19:16:15 +01:00
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class FetchTranslation : public BaseTLB::Translation
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{
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protected:
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TimingSimpleCPU *cpu;
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public:
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2009-04-09 07:21:27 +02:00
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FetchTranslation(TimingSimpleCPU *_cpu)
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: cpu(_cpu)
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2009-02-25 19:16:15 +01:00
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{}
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2011-02-12 01:29:35 +01:00
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void
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markDelayed()
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2011-02-12 01:29:35 +01:00
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{
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assert(cpu->_status == Running);
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cpu->_status = ITBWaitResponse;
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}
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2011-02-12 01:29:35 +01:00
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2009-04-09 07:21:27 +02:00
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void
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finish(Fault fault, RequestPtr req, ThreadContext *tc,
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BaseTLB::Mode mode)
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2009-02-25 19:16:15 +01:00
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{
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cpu->sendFetch(fault, req, tc);
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}
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};
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FetchTranslation fetchTranslation;
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2010-02-12 20:53:19 +01:00
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void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
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void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
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uint8_t *data, bool read);
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2009-02-25 19:16:15 +01:00
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void translationFault(Fault fault);
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void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
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void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
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RequestPtr req1, RequestPtr req2, RequestPtr req,
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uint8_t *data, bool read);
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2008-11-14 08:30:37 +01:00
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2008-11-10 06:56:28 +01:00
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bool handleReadPacket(PacketPtr pkt);
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// This function always implicitly uses dcache_pkt.
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bool handleWritePacket();
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2012-01-17 19:55:08 +01:00
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/**
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* A TimingCPUPort overrides the default behaviour of the
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* recvTiming and recvRetry and implements events for the
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* scheduling of handling of incoming packets in the following
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* cycle.
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*/
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class TimingCPUPort : public CpuPort
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2006-05-16 23:36:50 +02:00
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{
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public:
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2012-01-17 19:55:08 +01:00
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TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
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: CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
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2006-05-16 23:36:50 +02:00
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{ }
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protected:
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MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
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/**
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* Snooping a coherence request, do nothing.
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*/
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MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
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virtual void recvTimingSnoopReq(PacketPtr pkt) { }
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MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
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2012-01-17 19:55:08 +01:00
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TimingSimpleCPU* cpu;
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2006-07-21 01:00:40 +02:00
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struct TickEvent : public Event
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{
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2006-10-20 09:10:12 +02:00
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PacketPtr pkt;
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2006-07-21 01:00:40 +02:00
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TimingSimpleCPU *cpu;
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2012-01-17 19:55:08 +01:00
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TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
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2008-02-06 22:32:40 +01:00
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const char *description() const { return "Timing CPU tick"; }
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2006-10-20 09:10:12 +02:00
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void schedule(PacketPtr _pkt, Tick t);
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2006-07-21 01:00:40 +02:00
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};
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2012-07-09 18:35:31 +02:00
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EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent;
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2006-05-16 23:36:50 +02:00
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};
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2012-01-17 19:55:08 +01:00
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class IcachePort : public TimingCPUPort
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2006-05-16 23:36:50 +02:00
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{
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public:
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2012-01-17 19:55:08 +01:00
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IcachePort(TimingSimpleCPU *_cpu)
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2012-07-09 18:35:39 +02:00
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: TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
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2012-01-17 19:55:08 +01:00
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tickEvent(_cpu)
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2006-05-16 23:36:50 +02:00
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{ }
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protected:
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MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
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virtual bool recvTimingResp(PacketPtr pkt);
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2006-05-16 23:36:50 +02:00
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2006-05-31 00:57:42 +02:00
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virtual void recvRetry();
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2006-07-21 01:00:40 +02:00
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struct ITickEvent : public TickEvent
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{
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ITickEvent(TimingSimpleCPU *_cpu)
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: TickEvent(_cpu) {}
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void process();
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2008-02-06 22:32:40 +01:00
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const char *description() const { return "Timing CPU icache tick"; }
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2006-07-21 01:00:40 +02:00
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};
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ITickEvent tickEvent;
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2006-05-16 23:36:50 +02:00
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};
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2012-01-17 19:55:08 +01:00
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class DcachePort : public TimingCPUPort
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2006-05-16 23:36:50 +02:00
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{
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public:
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2012-01-17 19:55:08 +01:00
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DcachePort(TimingSimpleCPU *_cpu)
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2012-07-09 18:35:39 +02:00
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: TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
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tickEvent(_cpu)
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2006-05-16 23:36:50 +02:00
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{ }
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protected:
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MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
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virtual bool recvTimingResp(PacketPtr pkt);
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2006-05-16 23:36:50 +02:00
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2006-05-31 00:57:42 +02:00
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virtual void recvRetry();
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2006-07-21 01:00:40 +02:00
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struct DTickEvent : public TickEvent
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{
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DTickEvent(TimingSimpleCPU *_cpu)
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: TickEvent(_cpu) {}
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void process();
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2008-02-06 22:32:40 +01:00
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const char *description() const { return "Timing CPU dcache tick"; }
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2006-07-21 01:00:40 +02:00
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};
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DTickEvent tickEvent;
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2006-05-16 23:36:50 +02:00
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};
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IcachePort icachePort;
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DcachePort dcachePort;
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2006-10-20 09:10:12 +02:00
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PacketPtr ifetch_pkt;
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PacketPtr dcache_pkt;
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2006-05-16 23:36:50 +02:00
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2012-08-28 20:30:31 +02:00
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Tick previousCycle;
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2006-10-08 06:55:05 +02:00
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2012-02-24 17:42:00 +01:00
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protected:
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/** Return a reference to the data port. */
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virtual CpuPort &getDataPort() { return dcachePort; }
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2006-05-16 23:36:50 +02:00
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2012-02-24 17:42:00 +01:00
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/** Return a reference to the instruction port. */
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virtual CpuPort &getInstPort() { return icachePort; }
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public:
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2006-07-07 21:15:11 +02:00
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2006-05-16 23:36:50 +02:00
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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2006-07-13 02:22:07 +02:00
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virtual unsigned int drain(Event *drain_event);
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2006-06-30 01:45:24 +02:00
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virtual void resume();
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void switchOut();
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2006-05-16 23:36:50 +02:00
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void takeOverFrom(BaseCPU *oldCPU);
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|
2012-08-28 20:30:33 +02:00
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virtual void activateContext(ThreadID thread_num, Cycles delay);
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2012-01-31 18:05:52 +01:00
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virtual void suspendContext(ThreadID thread_num);
|
2006-05-16 23:36:50 +02:00
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|
2011-07-03 07:35:04 +02:00
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|
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
|
2010-08-13 15:16:02 +02:00
|
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|
2011-07-03 07:35:04 +02:00
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|
Fault writeMem(uint8_t *data, unsigned size,
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|
Addr addr, unsigned flags, uint64_t *res);
|
2010-08-13 15:16:02 +02:00
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|
2006-05-16 23:36:50 +02:00
|
|
|
void fetch();
|
2009-02-25 19:16:15 +01:00
|
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void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
|
2006-10-20 09:10:12 +02:00
|
|
|
void completeIfetch(PacketPtr );
|
2009-02-25 19:16:15 +01:00
|
|
|
void completeDataAccess(PacketPtr pkt);
|
2006-05-26 20:33:43 +02:00
|
|
|
void advanceInst(Fault fault);
|
2007-05-21 06:43:01 +02:00
|
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|
|
2012-09-25 18:49:40 +02:00
|
|
|
/** This function is used by the page table walker to determine if it could
|
|
|
|
* translate the a pending request or if the underlying request has been
|
|
|
|
* squashed. This always returns false for the simple timing CPU as it never
|
|
|
|
* executes any instructions speculatively.
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|
* @ return Is the current instruction squashed?
|
|
|
|
*/
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|
bool isSquashed() const { return false; }
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|
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|
2008-01-02 22:46:22 +01:00
|
|
|
/**
|
|
|
|
* Print state of address in memory system via PrintReq (for
|
|
|
|
* debugging).
|
|
|
|
*/
|
|
|
|
void printAddr(Addr a);
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|
|
|
|
2010-02-12 20:53:19 +01:00
|
|
|
/**
|
|
|
|
* Finish a DTB translation.
|
|
|
|
* @param state The DTB translation state.
|
|
|
|
*/
|
|
|
|
void finishTranslation(WholeTranslationState *state);
|
|
|
|
|
2006-06-30 01:45:24 +02:00
|
|
|
private:
|
2007-05-21 06:43:01 +02:00
|
|
|
|
|
|
|
typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
|
2008-10-27 23:18:04 +01:00
|
|
|
FetchEvent fetchEvent;
|
2007-05-21 06:43:01 +02:00
|
|
|
|
2007-10-01 08:55:27 +02:00
|
|
|
struct IprEvent : Event {
|
|
|
|
Packet *pkt;
|
|
|
|
TimingSimpleCPU *cpu;
|
|
|
|
IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
|
|
|
|
virtual void process();
|
2008-02-06 22:32:40 +01:00
|
|
|
virtual const char *description() const;
|
2007-10-01 08:55:27 +02:00
|
|
|
};
|
|
|
|
|
2006-07-05 23:59:33 +02:00
|
|
|
void completeDrain();
|
2006-05-16 23:36:50 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
#endif // __CPU_SIMPLE_TIMING_HH__
|