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Port: Align port names in C++ and Python

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This patch is a first step to align the port names used in the Python
world and the C++ world. Ultimately it serves to make the use of
config.json together with output from the simulation easier, including
post-processing of statistics.

Most notably, the CPU, cache, and bus is addressed in this patch, and
there might be other ports that should be updated accordingly. The
dash name separator has also been replaced with a "." which is what is
used to concatenate the names in python, and a separation is made
between the master and slave port in the bus.
This commit is contained in:
Andreas Hansson 2012-07-09 12:35:39 -04:00
parent 1c2ee987f3
commit b265d9925c
11 changed files with 25 additions and 22 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/cpu/inorder/cpu.cc
View file

@ -82,8 +82,9 @@ using namespace std;
using namespace TheISA;
using namespace ThePipeline;
InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
CpuPort(_cacheUnit->name() + "-cache-port", _cacheUnit->cpu),
InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit,
const std::string& name) :
CpuPort(_cacheUnit->name() + name, _cacheUnit->cpu),
cacheUnit(_cacheUnit)
{ }
@ -230,8 +231,8 @@ InOrderCPU::InOrderCPU(Params *params)
stageWidth(params->stageWidth),
resPool(new ResourcePool(this, params)),
timeBuffer(2 , 2),
dataPort(resPool->getDataUnit()),
instPort(resPool->getInstUnit()),
dataPort(resPool->getDataUnit(), ".dcache_port"),
instPort(resPool->getInstUnit(), ".icache_port"),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
system(params->system),

2
src/cpu/inorder/cpu.hh
View file

@ -165,7 +165,7 @@ class InOrderCPU : public BaseCPU
public:
/** Default constructor. */
CachePort(CacheUnit *_cacheUnit);
CachePort(CacheUnit *_cacheUnit, const std::string& name);
protected:

4
src/cpu/o3/cpu.hh
View file

@ -141,7 +141,7 @@ class FullO3CPU : public BaseO3CPU
public:
/** Default constructor. */
IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
: CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
: CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
{ }
protected:
@ -168,7 +168,7 @@ class FullO3CPU : public BaseO3CPU
public:
/** Default constructor. */
DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
: CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
: CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
{ }
protected:

3
src/cpu/simple/atomic.cc
View file

@ -105,7 +105,8 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
: BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
simulate_data_stalls(p->simulate_data_stalls),
simulate_inst_stalls(p->simulate_inst_stalls),
icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
icachePort(name() + ".icache_port", this),
dcachePort(name() + ".dcache_port", this),
fastmem(p->fastmem)
{
_status = Idle;

5
src/cpu/simple/timing.hh
View file

@ -178,7 +178,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
IcachePort(TimingSimpleCPU *_cpu)
: TimingCPUPort(_cpu->name() + "-iport", _cpu),
: TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
tickEvent(_cpu)
{ }
@ -206,7 +206,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
DcachePort(TimingSimpleCPU *_cpu)
: TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu)
: TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
tickEvent(_cpu)
{ }
protected:

2
src/dev/dma_device.cc
View file

@ -47,7 +47,7 @@
#include "sim/system.hh"
DmaPort::DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff)
: MasterPort(dev->name() + "-dma", dev), device(dev), sys(s),
: MasterPort(dev->name() + ".dma", dev), device(dev), sys(s),
masterId(s->getMasterId(dev->name())),
pendingCount(0), actionInProgress(0), drainEvent(NULL),
backoffTime(0), minBackoffDelay(min_backoff),

2
src/dev/io_device.cc
View file

@ -47,7 +47,7 @@
#include "sim/system.hh"
PioPort::PioPort(PioDevice *dev)
: SimpleTimingPort(dev->name() + "-pio", dev), device(dev)
: SimpleTimingPort(dev->name() + ".pio", dev), device(dev)
{
}

4
src/mem/bridge.cc
View file

@ -79,9 +79,9 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string &_name,
Bridge::Bridge(Params *p)
: MemObject(p),
slavePort(p->name + "-slave", this, masterPort, p->delay,
slavePort(p->name + ".slave", this, masterPort, p->delay,
p->nack_delay, p->resp_size, p->ranges),
masterPort(p->name + "-master", this, slavePort, p->delay, p->req_size),
masterPort(p->name + ".master", this, slavePort, p->delay, p->req_size),
ackWrites(p->write_ack), _params(p)
{
if (ackWrites)

4
src/mem/cache/cache_impl.hh vendored
View file

@ -72,9 +72,9 @@ Cache<TagStore>::Cache(const Params *p, TagStore *tags)
tempBlock = new BlkType();
tempBlock->data = new uint8_t[blkSize];
cpuSidePort = new CpuSidePort(p->name + "-cpu_side_port", this,
cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this,
"CpuSidePort");
memSidePort = new MemSidePort(p->name + "-mem_side_port", this,
memSidePort = new MemSidePort(p->name + ".mem_side", this,
"MemSidePort");
tags->setCache(this);

6
src/mem/coherent_bus.cc
View file

@ -62,7 +62,7 @@ CoherentBus::CoherentBus(const CoherentBusParams *p)
// vector ports, and the presence of the default port, the ports
// are enumerated starting from zero
for (int i = 0; i < p->port_master_connection_count; ++i) {
std::string portName = csprintf("%s-p%d", name(), i);
std::string portName = csprintf("%s.master[%d]", name(), i);
MasterPort* bp = new CoherentBusMasterPort(portName, *this, i);
masterPorts.push_back(bp);
}
@ -71,7 +71,7 @@ CoherentBus::CoherentBus(const CoherentBusParams *p)
// our corresponding master port
if (p->port_default_connection_count) {
defaultPortID = masterPorts.size();
std::string portName = csprintf("%s-default", name());
std::string portName = name() + ".default";
MasterPort* bp = new CoherentBusMasterPort(portName, *this,
defaultPortID);
masterPorts.push_back(bp);
@ -79,7 +79,7 @@ CoherentBus::CoherentBus(const CoherentBusParams *p)
// create the slave ports, once again starting at zero
for (int i = 0; i < p->port_slave_connection_count; ++i) {
std::string portName = csprintf("%s-p%d", name(), i);
std::string portName = csprintf("%s.slave[%d]", name(), i);
SlavePort* bp = new CoherentBusSlavePort(portName, *this, i);
slavePorts.push_back(bp);
}

6
src/mem/noncoherent_bus.cc
View file

@ -62,7 +62,7 @@ NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
// vector ports, and the presence of the default port, the ports
// are enumerated starting from zero
for (int i = 0; i < p->port_master_connection_count; ++i) {
std::string portName = csprintf("%s-p%d", name(), i);
std::string portName = csprintf("%s.master[%d]", name(), i);
MasterPort* bp = new NoncoherentBusMasterPort(portName, *this, i);
masterPorts.push_back(bp);
}
@ -71,7 +71,7 @@ NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
// our corresponding master port
if (p->port_default_connection_count) {
defaultPortID = masterPorts.size();
std::string portName = csprintf("%s-default", name());
std::string portName = name() + ".default";
MasterPort* bp = new NoncoherentBusMasterPort(portName, *this,
defaultPortID);
masterPorts.push_back(bp);
@ -79,7 +79,7 @@ NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
// create the slave ports, once again starting at zero
for (int i = 0; i < p->port_slave_connection_count; ++i) {
std::string portName = csprintf("%s-p%d", name(), i);
std::string portName = csprintf("%s.slave[%d]", name(), i);
SlavePort* bp = new NoncoherentBusSlavePort(portName, *this, i);
slavePorts.push_back(bp);
}