2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2016-02-24 10:16:59 +01:00
sim_seconds 47.389788 # Number of seconds simulated
sim_ticks 47389787812000 # Number of ticks simulated
final_tick 47389787812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-02-24 10:16:59 +01:00
host_inst_rate 198747 # Simulator instruction rate (inst/s)
host_op_rate 233711 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10002045644 # Simulator tick rate (ticks/s)
host_mem_usage 770464 # Number of bytes of host memory used
host_seconds 4738.01 # Real time elapsed on the host
sim_insts 941666991 # Number of instructions simulated
sim_ops 1107326086 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-02-24 10:16:59 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 242048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 235072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 4481952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 17644744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 24714560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 130176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 100480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2927520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 10373200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 13817664 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 418560 # Number of bytes read from this memory
system.physmem.bytes_read::total 75085976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 4481952 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2927520 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7409472 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 91336640 # Number of bytes written to this memory
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
2016-02-24 10:16:59 +01:00
system.physmem.bytes_written::total 91357224 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 3782 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3673 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 85983 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 275712 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 386165 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2034 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1570 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 45786 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 162094 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 215901 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6540 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1189240 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1427135 # Number of write requests responded to by this memory
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
2016-02-24 10:16:59 +01:00
system.physmem.num_writes::total 1429709 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 5108 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 4960 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 94576 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 372332 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 521517 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 2747 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2120 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 61775 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 218891 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 291575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8832 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1584434 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 94576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 61775 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 156352 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1927349 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
2016-02-24 10:16:59 +01:00
system.physmem.bw_write::total 1927783 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1927349 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 5108 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 4960 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 94576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 372766 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 521517 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 2747 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2120 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 61775 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 218891 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 291575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8832 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3512217 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1189240 # Number of read requests accepted
system.physmem.writeReqs 1429709 # Number of write requests accepted
system.physmem.readBursts 1189240 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1429709 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 76085248 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 26112 # Total number of bytes read from write queue
system.physmem.bytesWritten 91355968 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 75085976 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 91357224 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 408 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-02-24 10:16:59 +01:00
system.physmem.perBankRdBursts::0 75559 # Per bank write bursts
system.physmem.perBankRdBursts::1 80347 # Per bank write bursts
system.physmem.perBankRdBursts::2 72779 # Per bank write bursts
system.physmem.perBankRdBursts::3 76774 # Per bank write bursts
system.physmem.perBankRdBursts::4 67339 # Per bank write bursts
system.physmem.perBankRdBursts::5 74455 # Per bank write bursts
system.physmem.perBankRdBursts::6 73080 # Per bank write bursts
system.physmem.perBankRdBursts::7 76470 # Per bank write bursts
system.physmem.perBankRdBursts::8 66258 # Per bank write bursts
system.physmem.perBankRdBursts::9 90024 # Per bank write bursts
system.physmem.perBankRdBursts::10 66637 # Per bank write bursts
system.physmem.perBankRdBursts::11 75253 # Per bank write bursts
system.physmem.perBankRdBursts::12 70442 # Per bank write bursts
system.physmem.perBankRdBursts::13 75330 # Per bank write bursts
system.physmem.perBankRdBursts::14 75010 # Per bank write bursts
system.physmem.perBankRdBursts::15 73075 # Per bank write bursts
system.physmem.perBankWrBursts::0 90501 # Per bank write bursts
system.physmem.perBankWrBursts::1 95401 # Per bank write bursts
system.physmem.perBankWrBursts::2 90023 # Per bank write bursts
system.physmem.perBankWrBursts::3 92589 # Per bank write bursts
system.physmem.perBankWrBursts::4 84855 # Per bank write bursts
system.physmem.perBankWrBursts::5 90903 # Per bank write bursts
system.physmem.perBankWrBursts::6 89246 # Per bank write bursts
system.physmem.perBankWrBursts::7 91287 # Per bank write bursts
system.physmem.perBankWrBursts::8 85201 # Per bank write bursts
system.physmem.perBankWrBursts::9 88427 # Per bank write bursts
system.physmem.perBankWrBursts::10 83204 # Per bank write bursts
system.physmem.perBankWrBursts::11 90055 # Per bank write bursts
system.physmem.perBankWrBursts::12 88087 # Per bank write bursts
system.physmem.perBankWrBursts::13 89545 # Per bank write bursts
system.physmem.perBankWrBursts::14 89641 # Per bank write bursts
system.physmem.perBankWrBursts::15 88472 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-02-24 10:16:59 +01:00
system.physmem.numWrRetry 54 # Number of times write queue was full causing retry
system.physmem.totGap 47389786204500 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::3 25 # Read request sizes (log2)
2015-03-02 11:04:20 +01:00
system.physmem.readPktSize::4 21333 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-02-24 10:16:59 +01:00
system.physmem.readPktSize::6 1167882 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-02-24 10:16:59 +01:00
system.physmem.writePktSize::6 1427135 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 517223 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 309889 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 86868 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 62308 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 44912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 40171 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 37097 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 35200 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 31021 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 8620 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 4820 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 3062 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 2092 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1731 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1164 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 973 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 801 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 612 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 168 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 91 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-02-24 10:16:59 +01:00
system.physmem.wrQLenPdf::15 27129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 32204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 45048 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 50289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 57286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 61809 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 67754 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 74659 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 80821 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 85044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 90854 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 96241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 95504 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 100014 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 112663 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 99616 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 90045 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 84036 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 13635 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 10081 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 8296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 6959 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 5731 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 4894 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 4062 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 3275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 2801 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 2368 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 2057 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1553 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1352 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 979 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 831 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 620 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 596 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 417 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 389 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 175 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 154 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1166319 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 143.563495 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 97.562003 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 190.410734 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 788306 67.59% 67.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 223066 19.13% 86.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 56490 4.84% 91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 24874 2.13% 93.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 21482 1.84% 95.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 12177 1.04% 96.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8088 0.69% 97.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 4845 0.42% 97.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 26991 2.31% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1166319 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 68435 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 17.371564 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 68.388871 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 68432 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 68435 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 68435 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.858289 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.984573 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 74.928718 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-127 68190 99.64% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-255 151 0.22% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-383 21 0.03% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-511 14 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-639 8 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-767 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::768-895 5 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::896-1023 6 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1024-1151 3 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1152-1279 2 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1280-1407 2 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1536-1663 2 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1664-1791 4 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1792-1919 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2304-2431 4 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2432-2559 5 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2560-2687 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2688-2815 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2816-2943 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2944-3071 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3072-3199 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3584-3711 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3712-3839 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4096-4223 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4224-4351 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4864-4991 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5504-5631 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6656-6783 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::7680-7807 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 68435 # Writes before turning the bus around for reads
system.physmem.totQLat 53856464568 # Total ticks spent queuing
system.physmem.totMemAccLat 76147064568 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 5944160000 # Total ticks spent in databus transfers
system.physmem.avgQLat 45302.00 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-02-24 10:16:59 +01:00
system.physmem.avgMemAccLat 64052.00 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.61 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.93 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.93 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2014-12-23 15:31:20 +01:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
2016-02-24 10:16:59 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.02 # Average write queue length when enqueuing
system.physmem.readRowHits 898304 # Number of row buffer hits during reads
system.physmem.writeRowHits 551645 # Number of row buffer hits during writes
system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 38.65 # Row buffer hit rate for writes
system.physmem.avgGap 18094963.36 # Average gap between requests
system.physmem.pageHitRate 55.42 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 4527963720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2470615125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4655063400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4696736400 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1182204826065 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27396846617250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31690671909480 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.723752 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45576929865903 # Time in different power states
system.physmem_0.memoryStateTime::REF 1582448920000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-24 10:16:59 +01:00
system.physmem_0.memoryStateTime::ACT 230401885347 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-02-24 10:16:59 +01:00
system.physmem_1.actEnergy 4289407920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2340450750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4617779400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 4553055360 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1179475938810 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27399240378000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31689787097760 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.705081 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45580905738073 # Time in different power states
system.physmem_1.memoryStateTime::REF 1582448920000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-24 10:16:59 +01:00
system.physmem_1.memoryStateTime::ACT 226432462927 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory
2014-12-02 12:08:05 +01:00
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
2016-02-24 10:16:59 +01:00
system.cpu0.branchPred.lookups 148316317 # Number of BP lookups
system.cpu0.branchPred.condPredicted 98700135 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 7173487 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 104790534 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 69246034 # Number of BTB hits
2014-12-02 12:08:05 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-02-24 10:16:59 +01:00
system.cpu0.branchPred.BTBHitPct 66.080429 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 20257126 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 200970 # Number of incorrect RAS predictions.
2014-10-30 05:50:15 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walks 656451 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 656451 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15175 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105539 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 311743 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 344708 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2528.499484 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 15542.861274 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 341657 99.11% 99.11% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1528 0.44% 99.56% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 1197 0.35% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 153 0.04% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 49 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 98 0.03% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 19 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkWaitTime::total 344708 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 348998 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 21459.124408 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 17964.910208 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 23694.067201 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 343876 98.53% 98.53% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1141 0.33% 98.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2753 0.79% 99.65% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 227 0.07% 99.71% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.18% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 192 0.06% 99.95% # Table walker service (enqueue to completion) latency
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 104 0.03% 99.98% # Table walker service (enqueue to completion) latency
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 60 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 348998 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 578933652396 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.598699 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.548790 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 577357711896 99.73% 99.73% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 896498000 0.15% 99.88% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 316445000 0.05% 99.94% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 146967500 0.03% 99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 111299500 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 56334000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 19702000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 27806500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 847500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-21 1000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-25 1500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::26-27 2500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-29 1500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::30-31 15000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 578933652396 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 105540 87.43% 87.43% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 15175 12.57% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 120715 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656451 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656451 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120715 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120715 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 777166 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.read_hits 108931388 # DTB read hits
system.cpu0.dtb.read_misses 471682 # DTB read misses
system.cpu0.dtb.write_hits 89197418 # DTB write hits
system.cpu0.dtb.write_misses 184769 # DTB write misses
system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 44365 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 621 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 7762 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.perms_faults 42293 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 109403070 # DTB read accesses
system.cpu0.dtb.write_accesses 89382187 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.hits 198128806 # DTB hits
system.cpu0.dtb.misses 656451 # DTB misses
system.cpu0.dtb.accesses 198785257 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walks 90363 # Table walker walks requested
system.cpu0.itb.walker.walksLong 90363 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1091 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64708 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 10655 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 79708 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1706.014453 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 13195.811582 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767 78781 98.84% 98.84% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.56% 99.40% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303 48 0.06% 99.46% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071 68 0.09% 99.54% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839 262 0.33% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607 71 0.09% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 79708 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 76454 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 28396.329819 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23477.172430 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 32204.710724 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 73773 96.49% 96.49% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 162 0.21% 96.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 2119 2.77% 99.48% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 153 0.20% 99.68% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 135 0.18% 99.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 40 0.05% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 46 0.06% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 76454 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 441465071924 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.843066 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.363947 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 69311314608 15.70% 15.70% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 372126528316 84.29% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 24340500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 2776500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 112000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 441465071924 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 64708 98.34% 98.34% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 1091 1.66% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 65799 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 90363 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 90363 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 65799 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 65799 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 156162 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 234328898 # ITB inst hits
system.cpu0.itb.inst_misses 90363 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2016-02-24 10:16:59 +01:00
system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu0.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 32417 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-24 10:16:59 +01:00
system.cpu0.itb.perms_faults 232055 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-02-24 10:16:59 +01:00
system.cpu0.itb.inst_accesses 234419261 # ITB inst accesses
system.cpu0.itb.hits 234328898 # DTB hits
system.cpu0.itb.misses 90363 # DTB misses
system.cpu0.itb.accesses 234419261 # DTB accesses
system.cpu0.numCycles 866695747 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-02-24 10:16:59 +01:00
system.cpu0.fetch.icacheStallCycles 96427999 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 657049317 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 148316317 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 89503160 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 718043211 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 15454228 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2249933 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 346517 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 6840136 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 871998 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 916038 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 234095625 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 1822748 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 30173 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 833422946 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.924189 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.205964 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-02-24 10:16:59 +01:00
system.cpu0.fetch.rateDist::0 464359111 55.72% 55.72% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 143558418 17.23% 72.94% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 49834021 5.98% 78.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 175671396 21.08% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-02-24 10:16:59 +01:00
system.cpu0.fetch.rateDist::total 833422946 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.171128 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.758108 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 115740257 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 426691474 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 243999178 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 41506758 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5485279 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 21281954 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 2285386 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 681861872 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 24692274 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5485279 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 154051427 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 67882232 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 271801592 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 246639237 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 87563179 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 663764828 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 6318012 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 12552479 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 452890 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 885924 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 48607179 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 12032 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 634283684 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 1028589268 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 784350114 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 810310 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 573100551 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 61183133 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 17365169 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 15184195 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 83196676 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 108756528 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 92814116 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 10086189 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 8556855 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 639440304 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 17486234 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 645371130 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 2878587 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 57563182 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 37565263 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 301808 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 833422946 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.774362 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.052683 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-02-24 10:16:59 +01:00
system.cpu0.iq.issued_per_cycle::0 480257343 57.62% 57.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 149217372 17.90% 75.53% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 124187121 14.90% 90.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 71270973 8.55% 98.98% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 8484088 1.02% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 6049 0.00% 100.00% # Number of insts issued each cycle
2015-03-02 11:04:20 +01:00
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2015-03-02 11:04:20 +01:00
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-02-24 10:16:59 +01:00
system.cpu0.iq.issued_per_cycle::total 833422946 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-02-24 10:16:59 +01:00
system.cpu0.iq.fu_full::IntAlu 66055625 45.01% 45.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 69293 0.05% 45.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 22404 0.02% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 38927283 26.53% 71.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 41671380 28.40% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-02-24 10:16:59 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 440798988 68.30% 68.30% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1592862 0.25% 68.55% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 83426 0.01% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 82619 0.01% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 112232372 17.39% 85.96% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 90580861 14.04% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-02-24 10:16:59 +01:00
system.cpu0.iq.FU_type_0::total 645371130 # Type of FU issued
system.cpu0.iq.rate 0.744634 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 146746002 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.227382 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 2272436054 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 714094331 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 626839047 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1353741 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 552796 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 503202 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 791281833 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 835299 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 3004923 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-02-24 10:16:59 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 13275769 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 18782 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 159110 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 6200623 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-02-24 10:16:59 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 2963562 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 5149852 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-02-24 10:16:59 +01:00
system.cpu0.iew.iewSquashCycles 5485279 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 8917054 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 3122413 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 657057128 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-02-24 10:16:59 +01:00
system.cpu0.iew.iewDispLoadInsts 108756528 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 92814116 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 14923426 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 69667 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 2968943 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 159110 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2170447 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 3075539 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 5245986 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 637077586 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 108926469 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 7646279 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
2016-02-24 10:16:59 +01:00
system.cpu0.iew.exec_nop 130590 # number of nop insts executed
system.cpu0.iew.exec_refs 198124159 # number of memory reference insts executed
system.cpu0.iew.exec_branches 119913450 # Number of branches executed
system.cpu0.iew.exec_stores 89197690 # Number of stores executed
system.cpu0.iew.exec_rate 0.735065 # Inst execution rate
system.cpu0.iew.wb_sent 628157908 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 627342249 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 305063287 # num instructions producing a value
system.cpu0.iew.wb_consumers 500478465 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.723832 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.609543 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 50300993 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 17184426 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4931652 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 823863885 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.727503 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.534838 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-02-24 10:16:59 +01:00
system.cpu0.commit.committed_per_cycle::0 560826617 68.07% 68.07% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 136759290 16.60% 84.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 58156007 7.06% 91.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 19570368 2.38% 94.11% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 13861730 1.68% 95.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 9557005 1.16% 96.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 6407217 0.78% 97.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3899508 0.47% 98.20% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 14826143 1.80% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-02-24 10:16:59 +01:00
system.cpu0.commit.committed_per_cycle::total 823863885 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 510319417 # Number of instructions committed
system.cpu0.commit.committedOps 599363355 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
2016-02-24 10:16:59 +01:00
system.cpu0.commit.refs 182094252 # Number of memory references committed
system.cpu0.commit.loads 95480759 # Number of loads committed
system.cpu0.commit.membars 4094698 # Number of memory barriers committed
system.cpu0.commit.branches 113994539 # Number of branches committed
system.cpu0.commit.fp_insts 490256 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 549724602 # Number of committed integer instructions.
system.cpu0.commit.function_calls 15118537 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-02-24 10:16:59 +01:00
system.cpu0.commit.op_class_0::IntAlu 415786848 69.37% 69.37% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1342849 0.22% 69.60% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 66347 0.01% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 73059 0.01% 69.62% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 95480759 15.93% 85.55% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 86613493 14.45% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-02-24 10:16:59 +01:00
system.cpu0.commit.op_class_0::total 599363355 # Class of committed instruction
system.cpu0.commit.bw_lim_events 14826143 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1454251951 # The number of ROB reads
system.cpu0.rob.rob_writes 1308847090 # The number of ROB writes
system.cpu0.timesIdled 1090671 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 33272801 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 93912870328 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 510319417 # Number of Instructions Simulated
system.cpu0.committedOps 599363355 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.698340 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.698340 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.588810 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.588810 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 752522588 # number of integer regfile reads
system.cpu0.int_regfile_writes 446228364 # number of integer regfile writes
system.cpu0.fp_regfile_reads 791452 # number of floating regfile reads
system.cpu0.fp_regfile_writes 475504 # number of floating regfile writes
system.cpu0.cc_regfile_reads 139593627 # number of cc regfile reads
system.cpu0.cc_regfile_writes 140336082 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1450242581 # number of misc regfile reads
system.cpu0.misc_regfile_writes 17300190 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 6628748 # number of replacements
system.cpu0.dcache.tags.tagsinuse 507.898673 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 168544062 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6629257 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 25.424276 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit.
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.898673 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991990 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.991990 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 377708512 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 377708512 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 88226592 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 88226592 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 75029005 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 75029005 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 221757 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 221757 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177850 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 177850 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1970217 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1970217 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2022489 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 2022489 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 163255597 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 163255597 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 163477354 # number of overall hits
system.cpu0.dcache.overall_hits::total 163477354 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 7367994 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7367994 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 8340746 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 8340746 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 804684 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 804684 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 826218 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 826218 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 297937 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 297937 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 206643 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 206643 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 15708740 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 15708740 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 16513424 # number of overall misses
system.cpu0.dcache.overall_misses::total 16513424 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 129957875000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 129957875000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 197611984656 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 197611984656 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 55152577242 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 55152577242 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4832056500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 4832056500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5849414000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 5849414000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5216000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5216000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 327569859656 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 327569859656 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 327569859656 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 327569859656 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 95594586 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 95594586 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 83369751 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 83369751 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1026441 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1026441 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1004068 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1004068 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2268154 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2268154 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2229132 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2229132 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 178964337 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 178964337 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 179990778 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 179990778 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.077075 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.077075 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.100045 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.100045 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783955 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783955 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822871 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822871 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131357 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131357 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092701 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092701 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.087776 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.087776 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.091746 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.091746 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17638.162436 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17638.162436 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23692.363328 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23692.363328 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66753.056992 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66753.056992 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16218.383417 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16218.383417 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28306.857721 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28306.857721 # average StoreCondReq miss latency
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20852.713818 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20852.713818 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19836.580206 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 19836.580206 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 17065024 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 30777617 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 770223 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 827793 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 22.155952 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 37.180330 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.writebacks::writebacks 6628874 # number of writebacks
system.cpu0.dcache.writebacks::total 6628874 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3770079 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 3770079 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6700876 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 6700876 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4178 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 4178 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 152938 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 152938 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 10470955 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 10470955 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 10470955 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 10470955 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3597915 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3597915 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1639870 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1639870 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 797671 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 797671 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 822040 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 822040 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 144999 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 144999 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 206643 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 206643 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5237785 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 5237785 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 6035456 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 6035456 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19715 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19715 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21606 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21606 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 41321 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 41321 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 58751059000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 58751059000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 44752175448 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 44752175448 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 21047920500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21047920500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 54096896242 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 54096896242 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2128355000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2128355000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5642835000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5642835000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5152000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5152000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 103503234448 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 103503234448 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 124551154948 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 124551154948 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3829698500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3829698500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4085083000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4085083000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7914781500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7914781500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037637 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037637 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019670 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019670 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.777123 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.777123 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818709 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818709 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063928 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063928 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092701 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092701 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029267 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029267 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033532 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16329.195937 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16329.195937 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27290.075096 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27290.075096 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26386.718961 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26386.718961 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65808.106956 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65808.106956 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14678.411575 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14678.411575 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27307.167434 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27307.167434 # average StoreCondReq mshr miss latency
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19760.878778 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19760.878778 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20636.577410 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20636.577410 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194253.030687 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194253.030687 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189071.693048 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189071.693048 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191543.803393 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191543.803393 # average overall mshr uncacheable latency
2014-12-02 12:08:05 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.replacements 6540239 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.944561 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 227144563 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 6540751 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 34.727597 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 18012149000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.944561 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999892 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.tag_accesses 474674738 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 474674738 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 227144563 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 227144563 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 227144563 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 227144563 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 227144563 # number of overall hits
system.cpu0.icache.overall_hits::total 227144563 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 6922414 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 6922414 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 6922414 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 6922414 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 6922414 # number of overall misses
system.cpu0.icache.overall_misses::total 6922414 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 78815703700 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 78815703700 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 78815703700 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 78815703700 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 78815703700 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 78815703700 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 234066977 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 234066977 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 234066977 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 234066977 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 234066977 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 234066977 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029575 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.029575 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029575 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.029575 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029575 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.029575 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11385.580767 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11385.580767 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11385.580767 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11385.580767 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 12205805 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 1929 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 815036 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.975786 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 148.384615 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
2016-02-24 10:16:59 +01:00
system.cpu0.icache.writebacks::writebacks 6540239 # number of writebacks
system.cpu0.icache.writebacks::total 6540239 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 381630 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 381630 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 381630 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 381630 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 381630 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 381630 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6540784 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 6540784 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6540784 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 6540784 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6540784 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 6540784 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 70913768580 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 70913768580 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 70913768580 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 70913768580 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 70913768580 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 70913768580 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027944 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.027944 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.027944 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10841.784193 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10841.784193 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10841.784193 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.prefetcher.num_hwpf_issued 9036202 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 9047325 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 9983 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.prefetcher.pfSpanPage 1166339 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 3033682 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16193.393040 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 19026764 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 3049439 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.239431 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 3423113000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15201.196894 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 62.932138 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 78.683801 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000068 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 850.580138 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.927807 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003841 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004802 # Average percentage of cache occupancy
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051915 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.988366 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1326 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14340 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 70 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 174 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 642 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 440 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 70 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 900 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4799 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4876 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3646 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080933 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.875244 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 451755433 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 451755433 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 669148 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 205466 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 874614 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 4337694 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 4337694 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 8829361 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 8829361 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1023 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 1023 # number of UpgradeReq hits
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1003467 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 1003467 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5907946 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 5907946 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3394515 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 3394515 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175024 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 175024 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 669148 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 205466 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 5907946 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 4397982 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 11180542 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 669148 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 205466 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 5907946 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 4397982 # number of overall hits
system.cpu0.l2cache.overall_hits::total 11180542 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 14498 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10801 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 25299 # number of ReadReq misses
system.cpu0.l2cache.WritebackDirty_misses::writebacks 6 # number of WritebackDirty misses
system.cpu0.l2cache.WritebackDirty_misses::total 6 # number of WritebackDirty misses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses
system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 283162 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 283162 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 206636 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 206636 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 363386 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 363386 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 632821 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 632821 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1142961 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 1142961 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 644935 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 644935 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 14498 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10801 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 632821 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1506347 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 2164467 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 14498 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10801 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 632821 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1506347 # number of overall misses
system.cpu0.l2cache.overall_misses::total 2164467 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 831200000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 735223500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 1566423500 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3616020000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 3616020000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2092116500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2092116500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5056000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5056000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 25090830000 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 25090830000 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 25302734498 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 25302734498 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 52461352979 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 52461352979 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 386032000 # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total 386032000 # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 831200000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 735223500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 25302734498 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 77552182979 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 104421340977 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 831200000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 735223500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 25302734498 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 77552182979 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 104421340977 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 683646 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 216267 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 899913 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4337700 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 4337700 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 8829363 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 8829363 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 284185 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 284185 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 206637 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 206637 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1366853 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1366853 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6540767 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 6540767 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4537476 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 4537476 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819959 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 819959 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 683646 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 216267 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 6540767 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 5904329 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 13345009 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 683646 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 216267 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 6540767 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 5904329 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 13345009 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021207 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049943 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.028113 # miss rate for ReadReq accesses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996400 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996400 # miss rate for UpgradeReq accesses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.265856 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.265856 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.096750 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.096750 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.251894 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.251894 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.786545 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.786545 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021207 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049943 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.096750 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.255126 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.162193 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021207 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049943 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.096750 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.255126 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.162193 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 57332.045799 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 68069.947227 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 61916.419621 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12770.145712 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12770.145712 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10124.646722 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10124.646722 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 842666.666667 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 842666.666667 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69047.321581 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69047.321581 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39984.031026 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39984.031026 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45899.512738 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45899.512738 # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 598.559545 # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 598.559545 # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 57332.045799 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 68069.947227 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39984.031026 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 51483.611000 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 48243.443294 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 57332.045799 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 68069.947227 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39984.031026 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 51483.611000 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 48243.443294 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 2497 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.blocked::no_mshrs 23 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 108.565217 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.writebacks::writebacks 1894575 # number of writebacks
system.cpu0.l2cache.writebacks::total 1894575 # number of writebacks
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 5 # number of ReadReq MSHR hits
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 193 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 198 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 69860 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 69860 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 7488 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 7488 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 6 # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 5 # number of demand (read+write) MSHR hits
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 193 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 77348 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 77552 # number of demand (read+write) MSHR hits
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 5 # number of overall MSHR hits
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 193 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 77348 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 77552 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 14493 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10608 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 25101 # number of ReadReq MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 6 # number of WritebackDirty MSHR misses
system.cpu0.l2cache.WritebackDirty_mshr_misses::total 6 # number of WritebackDirty MSHR misses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses
system.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 934637 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 934637 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 283162 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 283162 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 206636 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 206636 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 293526 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 293526 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 632815 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 632815 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1135473 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1135473 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 644929 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total 644929 # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 14493 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10608 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 632815 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1428999 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 2086915 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 14493 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10608 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 632815 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1428999 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 934637 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 3021552 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19715 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 41008 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21606 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21606 # number of WriteReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 41321 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 62614 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 659971500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1404121000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 78126139116 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 78126139116 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 8227819495 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 8227819495 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4089973495 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4089973495 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4672000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4672000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 18739186500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 18739186500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21505748998 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21505748998 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 45049566980 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 45049566980 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 46970391994 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 46970391994 # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 659971500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21505748998 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 63788753480 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 86698623478 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 659971500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21505748998 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 63788753480 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 78126139116 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 164824762594 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3671826500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6451909000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3917316467 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3917316467 # number of WriteReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7589142967 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10369225467 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027893 # mshr miss rate for ReadReq accesses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996400 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996400 # mshr miss rate for UpgradeReq accesses
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.214746 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.214746 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096749 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.250243 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250243 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.786538 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.786538 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242026 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156382 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242026 # mshr miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226418 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 55938.847058 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83589.820557 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29056.933822 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29056.933822 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19793.131376 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19793.131376 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 778666.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 778666.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63841.657979 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63841.657979 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33984.259220 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39674.714397 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39674.714397 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 72830.330151 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 72830.330151 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44638.767053 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41543.916967 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44638.767053 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 54549.702469 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186245.320822 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157332.935037 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181306.880820 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181306.880820 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183663.100288 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165605.542962 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.cpu0.toL2Bus.snoop_filter.tot_requests 27325930 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14061042 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238708 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238208 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq 1035490 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 12208665 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 21607 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 21606 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 6237038 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 8831409 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 2977562 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 1194066 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 497340 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368088 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 556890 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1397051 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1373685 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6540784 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5522441 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 877204 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 819959 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19664376 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21309678 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 452328 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1442065 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 42868447 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 837525072 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 808748037 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1730136 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5469168 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1653472413 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 7780555 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 22331081 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.118319 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.323054 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.cpu0.toL2Bus.snoop_fanout::0 19689398 88.17% 88.17% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2641183 11.83% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 500 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.cpu0.toL2Bus.snoop_fanout::total 22331081 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 27171038408 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu0.toL2Bus.snoopLayer0.occupancy 185981894 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu0.toL2Bus.respLayer0.occupancy 9839167037 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu0.toL2Bus.respLayer1.occupancy 9551310776 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu0.toL2Bus.respLayer2.occupancy 236496624 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu0.toL2Bus.respLayer3.occupancy 759104112 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu1.branchPred.lookups 126248667 # Number of BP lookups
system.cpu1.branchPred.condPredicted 84543955 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 6151855 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 88859655 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 57842551 # Number of BTB hits
2014-10-30 05:50:15 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-02-24 10:16:59 +01:00
system.cpu1.branchPred.BTBHitPct 65.094278 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 16827370 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 172583 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walks 548057 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 548057 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11885 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88263 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 254796 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 293261 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2461.776370 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 15099.601662 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-131071 292248 99.65% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-262143 874 0.30% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-393215 111 0.04% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-524287 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::655360-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 293261 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 284367 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 20156.804411 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 17511.621467 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 17128.200610 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 282098 99.20% 99.20% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 636 0.22% 99.43% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1232 0.43% 99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 88 0.03% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 184 0.06% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 74 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 284367 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 458679401608 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.570209 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.555852 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 457501852108 99.74% 99.74% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3 610883500 0.13% 99.88% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5 255647500 0.06% 99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7 124159500 0.03% 99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9 89499500 0.02% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11 56037000 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13 17511000 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15 23464500 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17 345500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 458679401608 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 88263 88.13% 88.13% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 11885 11.87% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 100148 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 548057 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 548057 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 100148 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 100148 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 648205 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.read_hits 92943696 # DTB read hits
system.cpu1.dtb.read_misses 375200 # DTB read misses
system.cpu1.dtb.write_hits 76575759 # DTB write hits
system.cpu1.dtb.write_misses 172857 # DTB write misses
system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 35565 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 273 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 6009 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.perms_faults 39938 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 93318896 # DTB read accesses
system.cpu1.dtb.write_accesses 76748616 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.hits 169519455 # DTB hits
system.cpu1.dtb.misses 548057 # DTB misses
system.cpu1.dtb.accesses 170067512 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walks 81693 # Table walker walks requested
system.cpu1.itb.walker.walksLong 81693 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 804 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58754 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 9814 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 71879 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1351.430877 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 10594.939676 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767 71238 99.11% 99.11% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535 384 0.53% 99.64% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303 26 0.04% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071 48 0.07% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839 113 0.16% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607 53 0.07% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
2016-02-10 10:08:27 +01:00
system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::458752-491519 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 71879 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 69372 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 25253.272214 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 22467.195437 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 22091.390725 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 68357 98.54% 98.54% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 80 0.12% 98.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 757 1.09% 99.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 76 0.11% 99.85% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 69372 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 407136400556 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.838375 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.368280 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 65826877124 16.17% 16.17% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 341288268432 83.83% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 19212000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 1863000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 150500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 29500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 407136400556 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 58754 98.65% 98.65% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 804 1.35% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 59558 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81693 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81693 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59558 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59558 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 141251 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 198485673 # ITB inst hits
system.cpu1.itb.inst_misses 81693 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2016-02-24 10:16:59 +01:00
system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu1.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 25168 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-24 10:16:59 +01:00
system.cpu1.itb.perms_faults 206844 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-02-24 10:16:59 +01:00
system.cpu1.itb.inst_accesses 198567366 # ITB inst accesses
system.cpu1.itb.hits 198485673 # DTB hits
system.cpu1.itb.misses 81693 # DTB misses
system.cpu1.itb.accesses 198567366 # DTB accesses
system.cpu1.numCycles 706357244 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-02-24 10:16:59 +01:00
system.cpu1.fetch.icacheStallCycles 79757859 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 558826368 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 126248667 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 74669921 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 588203471 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 13287396 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 1859618 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 301703 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 6107940 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 765855 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 800562 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 198257766 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 1531728 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 28220 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 684440706 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.958907 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.215902 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-02-24 10:16:59 +01:00
system.cpu1.fetch.rateDist::0 370240796 54.09% 54.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 122429423 17.89% 71.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 41426108 6.05% 78.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 150344379 21.97% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-02-24 10:16:59 +01:00
system.cpu1.fetch.rateDist::total 684440706 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.178732 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.791138 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 96144629 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 340788757 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 207685438 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 35085697 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 4736185 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 17812454 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 1944962 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 579921351 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 21338656 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 4736185 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 128930138 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 49237812 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 228920665 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 209565208 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 63050698 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 564205236 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 5454916 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 10256691 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 240677 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 354262 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 30213880 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 11171 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 537096625 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 872562806 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 667157366 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 686134 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 483982102 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 53114517 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 15098547 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 13303136 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 70645723 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 92937642 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 79702799 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 8581032 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 7318731 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 542982721 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 15290733 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 547999845 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 2492376 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 50310716 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 32527030 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 258040 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 684440706 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.800653 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.060998 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-02-24 10:16:59 +01:00
system.cpu1.iq.issued_per_cycle::0 384384408 56.16% 56.16% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 127393239 18.61% 74.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 104776738 15.31% 90.08% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 60496264 8.84% 98.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 7385947 1.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 4110 0.00% 100.00% # Number of insts issued each cycle
2014-12-23 15:31:20 +01:00
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-12-23 15:31:20 +01:00
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-02-24 10:16:59 +01:00
system.cpu1.iq.issued_per_cycle::total 684440706 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-02-24 10:16:59 +01:00
system.cpu1.iq.fu_full::IntAlu 55139379 44.00% 44.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 46977 0.04% 44.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 11488 0.01% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 7 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 33502933 26.74% 70.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 36611567 29.22% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-02-24 10:16:59 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 373183107 68.10% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1202540 0.22% 68.32% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 67362 0.01% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 42387 0.01% 68.34% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 95737452 17.47% 85.81% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 77766935 14.19% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-02-24 10:16:59 +01:00
system.cpu1.iq.FU_type_0::total 547999845 # Type of FU issued
system.cpu1.iq.rate 0.775811 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 125312351 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.228672 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1907132649 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 608283649 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 532258075 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1112472 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 437179 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 408398 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 672616839 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 695346 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 2459057 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-02-24 10:16:59 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 11465284 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 14564 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 137615 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 5482962 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-02-24 10:16:59 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 2463728 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 4019009 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-02-24 10:16:59 +01:00
system.cpu1.iew.iewSquashCycles 4736185 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 6263173 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 2375395 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 558389408 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-02-24 10:16:59 +01:00
system.cpu1.iew.iewDispLoadInsts 92937642 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 79702799 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 13061254 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 63231 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 2253383 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 137615 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 1902304 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2611236 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 4513540 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 540870869 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 92937926 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 6592838 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
2016-02-24 10:16:59 +01:00
system.cpu1.iew.exec_nop 115954 # number of nop insts executed
system.cpu1.iew.exec_refs 169513519 # number of memory reference insts executed
system.cpu1.iew.exec_branches 101590895 # Number of branches executed
system.cpu1.iew.exec_stores 76575593 # Number of stores executed
system.cpu1.iew.exec_rate 0.765719 # Inst execution rate
system.cpu1.iew.wb_sent 533377466 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 532666473 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 257434056 # num instructions producing a value
system.cpu1.iew.wb_consumers 422362739 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.754104 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.609509 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 44033715 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 15032693 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4244342 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 676109975 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.751302 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.553770 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-02-24 10:16:59 +01:00
system.cpu1.commit.committed_per_cycle::0 452513238 66.93% 66.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 117033560 17.31% 84.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 49159205 7.27% 91.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 16297256 2.41% 93.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 11766410 1.74% 95.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 7925929 1.17% 96.83% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5496145 0.81% 97.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3299018 0.49% 98.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 12619214 1.87% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-02-24 10:16:59 +01:00
system.cpu1.commit.committed_per_cycle::total 676109975 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 431347574 # Number of instructions committed
system.cpu1.commit.committedOps 507962731 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2016-02-24 10:16:59 +01:00
system.cpu1.commit.refs 155692194 # Number of memory references committed
system.cpu1.commit.loads 81472357 # Number of loads committed
system.cpu1.commit.membars 3613840 # Number of memory barriers committed
system.cpu1.commit.branches 96395557 # Number of branches committed
system.cpu1.commit.fp_insts 400161 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 466077725 # Number of committed integer instructions.
system.cpu1.commit.function_calls 12507771 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-02-24 10:16:59 +01:00
system.cpu1.commit.op_class_0::IntAlu 351213617 69.14% 69.14% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 966298 0.19% 69.33% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 53161 0.01% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 37419 0.01% 69.35% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 81472357 16.04% 85.39% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 74219837 14.61% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-02-24 10:16:59 +01:00
system.cpu1.commit.op_class_0::total 507962731 # Class of committed instruction
system.cpu1.commit.bw_lim_events 12619214 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1211577193 # The number of ROB reads
system.cpu1.rob.rob_writes 1112287280 # The number of ROB writes
system.cpu1.timesIdled 906823 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 21916538 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 94073218429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 431347574 # Number of Instructions Simulated
system.cpu1.committedOps 507962731 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.637559 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.637559 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.610665 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.610665 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 639350275 # number of integer regfile reads
system.cpu1.int_regfile_writes 378298878 # number of integer regfile writes
system.cpu1.fp_regfile_reads 675031 # number of floating regfile reads
system.cpu1.fp_regfile_writes 302028 # number of floating regfile writes
system.cpu1.cc_regfile_reads 116956107 # number of cc regfile reads
system.cpu1.cc_regfile_writes 117682636 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1203449961 # number of misc regfile reads
system.cpu1.misc_regfile_writes 15173732 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 5181385 # number of replacements
system.cpu1.dcache.tags.tagsinuse 448.144658 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 145015910 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5181896 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 27.985106 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8482612216500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.144658 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875283 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.875283 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 322931039 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 322931039 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 75698887 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 75698887 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 64698314 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 64698314 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177630 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 177630 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 137318 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 137318 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768516 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1768516 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1769874 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1769874 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 140397201 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 140397201 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 140574831 # number of overall hits
system.cpu1.dcache.overall_hits::total 140574831 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 6071314 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 6071314 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 6974888 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 6974888 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 655927 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 655927 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 434582 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 434582 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243161 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 243161 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198274 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 198274 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 13046202 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 13046202 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 13702129 # number of overall misses
system.cpu1.dcache.overall_misses::total 13702129 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101097830500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 101097830500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 149656092437 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 149656092437 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16022463739 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 16022463739 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3928870000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 3928870000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5496174000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 5496174000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4605500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4605500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 250753922937 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 250753922937 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 250753922937 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 250753922937 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 81770201 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 81770201 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 71673202 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 71673202 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 833557 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 833557 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 571900 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 571900 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2011677 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 2011677 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1968148 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1968148 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 153443403 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 153443403 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 154276960 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 154276960 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074248 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.074248 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.097315 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.097315 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.786901 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.786901 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.759892 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.759892 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120875 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120875 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100741 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100741 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085023 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.085023 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088815 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.088815 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16651.721604 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16651.721604 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21456.415133 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21456.415133 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36868.677808 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36868.677808 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16157.484136 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16157.484136 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27720.094415 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27720.094415 # average StoreCondReq miss latency
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-02-24 10:16:59 +01:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19220.453810 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19220.453810 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18300.362151 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18300.362151 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 4223664 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 23883166 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 349910 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 702949 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.070715 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 33.975674 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2016-02-24 10:16:59 +01:00
system.cpu1.dcache.writebacks::writebacks 5181409 # number of writebacks
system.cpu1.dcache.writebacks::total 5181409 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3107506 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 3107506 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5642769 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 5642769 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3498 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 3498 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 127094 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 127094 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 8750275 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 8750275 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 8750275 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 8750275 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2963808 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2963808 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1332119 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1332119 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 655846 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 655846 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 431084 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 431084 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116067 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116067 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198274 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 198274 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4295927 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4295927 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 4951773 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 4951773 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 18536 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 18536 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16538 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16538 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 35074 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 35074 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 45006607000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 45006607000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 31827699093 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 31827699093 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16353139500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16353139500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15385116239 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15385116239 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1766523500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1766523500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5297954000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5297954000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4551500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4551500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 76834306093 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 76834306093 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93187445593 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 93187445593 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3073252500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3073252500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2816431000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2816431000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5889683500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5889683500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036246 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036246 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018586 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018586 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.786804 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.786804 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.753775 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.753775 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057697 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057697 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100741 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100741 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027997 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.027997 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032097 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.032097 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15185.398987 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15185.398987 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23892.534445 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23892.534445 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24934.419818 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24934.419818 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35689.369680 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35689.369680 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15219.860081 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15219.860081 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26720.366765 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26720.366765 # average StoreCondReq mshr miss latency
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-02-24 10:16:59 +01:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17885.384480 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17885.384480 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18819.005959 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18819.005959 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165799.120630 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165799.120630 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 170300.580481 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170300.580481 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167921.637110 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167921.637110 # average overall mshr uncacheable latency
2014-12-02 12:08:05 +01:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.cpu1.icache.tags.replacements 5433139 # number of replacements
system.cpu1.icache.tags.tagsinuse 501.652394 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 192499091 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 5433651 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 35.427209 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8522355919000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.652394 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979790 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.979790 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-24 10:16:59 +01:00
system.cpu1.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-02-24 10:16:59 +01:00
system.cpu1.icache.tags.tag_accesses 401935440 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 401935440 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 192499091 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 192499091 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 192499091 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 192499091 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 192499091 # number of overall hits
system.cpu1.icache.overall_hits::total 192499091 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 5751797 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 5751797 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 5751797 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 5751797 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 5751797 # number of overall misses
system.cpu1.icache.overall_misses::total 5751797 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64772051533 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 64772051533 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 64772051533 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 64772051533 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 64772051533 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 64772051533 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 198250888 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 198250888 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 198250888 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 198250888 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 198250888 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 198250888 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029013 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.029013 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029013 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.029013 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029013 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.029013 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11261.185249 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 11261.185249 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11261.185249 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 11261.185249 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11261.185249 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 11261.185249 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 9932539 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 584 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 679779 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.611424 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 83.428571 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
2016-02-24 10:16:59 +01:00
system.cpu1.icache.writebacks::writebacks 5433139 # number of writebacks
system.cpu1.icache.writebacks::total 5433139 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 318133 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 318133 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 318133 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 318133 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 318133 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 318133 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5433664 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 5433664 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 5433664 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 5433664 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 5433664 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 5433664 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58335043744 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 58335043744 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58335043744 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 58335043744 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58335043744 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 58335043744 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9645998 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9645998 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9645998 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 9645998 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027408 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.027408 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.027408 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10735.857746 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 143970.119403 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 143970.119403 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7104582 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 7110323 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 5229 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.prefetcher.pfSpanPage 868037 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 2129197 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13328.245122 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 15739911 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2145331 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 7.336822 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 9958132586000 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12434.905270 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 47.585138 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 48.632741 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000002 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 797.121970 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.758966 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002904 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002968 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048652 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.813492 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1216 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14843 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 201 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 613 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 375 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1347 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6023 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4378 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2999 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074219 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905945 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 365454297 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 365454297 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 563276 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186249 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 749525 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3287486 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3287486 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 7325630 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 7325630 # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 588 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 588 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 828832 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 828832 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4887396 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 4887396 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2758073 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2758073 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 186873 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 186873 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 563276 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186249 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 4887396 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3586905 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 9223826 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 563276 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186249 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 4887396 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3586905 # number of overall hits
system.cpu1.l2cache.overall_hits::total 9223826 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11569 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8316 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 19885 # number of ReadReq misses
2016-02-10 10:08:27 +01:00
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2016-02-24 10:16:59 +01:00
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2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses
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2016-02-24 10:16:59 +01:00
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2016-02-10 10:08:27 +01:00
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2014-10-30 05:50:15 +01:00
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system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2016-02-24 10:16:59 +01:00
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2014-10-30 05:50:15 +01:00
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2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
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2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 87.375000 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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2016-02-24 10:16:59 +01:00
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2016-02-10 10:08:27 +01:00
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2016-02-24 10:16:59 +01:00
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2015-05-05 09:22:39 +02:00
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2016-02-24 10:16:59 +01:00
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2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 35074 # number of overall MSHR uncacheable misses
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system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 45381598688 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 45381598688 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7175483993 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7175483993 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3808164996 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3808164996 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4145999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4145999 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11475367999 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11475367999 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17321524000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17321524000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 33026830978 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 33026830978 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11580370998 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11580370998 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 479105500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 347671000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17321524000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 44502198977 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 62650499477 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 479105500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 347671000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17321524000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 44502198977 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 45381598688 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 108032098165 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9142500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2924847500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2933990000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2692324500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2692324500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9142500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5617172000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5626314500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025585 # mshr miss rate for ReadReq accesses
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997423 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997423 # mshr miss rate for UpgradeReq accesses
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220198 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220198 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100533 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.259697 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.259697 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.564482 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.564482 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250625 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161131 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250625 # mshr miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-02-24 10:16:59 +01:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227681 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42000.330201 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 61725.447981 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31534.767177 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31534.767177 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19207.062102 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19207.062102 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 829199.800000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 829199.800000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46834.031226 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46834.031226 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31709.187167 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34078.669100 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34078.669100 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 47809.112331 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 47809.112331 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35194.853490 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42949.626773 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157792.808589 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157715.959791 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162796.257105 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162796.257105 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 160152.021440 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 160106.841012 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.cpu1.toL2Bus.snoop_filter.tot_requests 22091106 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11384004 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1936993 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1936645 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 348 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq 874786 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 10136227 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 16538 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 16538 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4413805 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 7327056 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 2612396 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 936034 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 441152 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362021 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 491027 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1142611 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1118724 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5433664 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4777910 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 490221 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 429103 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16300596 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16818339 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 407716 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1217877 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 34744528 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 695476144 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 648316997 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1556520 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4598760 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1349948421 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 6442205 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 18213720 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.125270 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.331082 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.cpu1.toL2Bus.snoop_fanout::0 15932436 87.47% 87.47% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 2280936 12.52% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 348 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.cpu1.toL2Bus.snoop_fanout::total 18213720 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 21942621967 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu1.toL2Bus.snoopLayer0.occupancy 185589939 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu1.toL2Bus.respLayer0.occupancy 8156255052 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu1.toL2Bus.respLayer1.occupancy 7729530656 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu1.toL2Bus.respLayer2.occupancy 213583628 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu1.toL2Bus.respLayer3.occupancy 643750548 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.trans_dist::ReadReq 40360 # Transaction distribution
system.iobus.trans_dist::ReadResp 40360 # Transaction distribution
system.iobus.trans_dist::WriteReq 136653 # Transaction distribution
system.iobus.trans_dist::WriteResp 136653 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47814 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count_system.bridge.master::total 122696 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231250 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231250 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count::total 354026 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47834 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size_system.bridge.master::total 155826 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7339016 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:05 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size::total 7496928 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 37078503 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer23.occupancy 24630000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer24.occupancy 36390000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer25.occupancy 567310169 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.respLayer0.occupancy 92774000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.respLayer3.occupancy 147946000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iocache.tags.replacements 115606 # number of replacements
system.iocache.tags.tagsinuse 11.303294 # Cycle average of tags in use
2015-12-05 01:11:25 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2016-02-24 10:16:59 +01:00
system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2016-02-24 10:16:59 +01:00
system.iocache.tags.warmup_cycle 9121340835000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.838171 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.465123 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.239886 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.466570 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.706456 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-02-24 10:16:59 +01:00
system.iocache.tags.tag_accesses 1040982 # Number of tag accesses
system.iocache.tags.data_accesses 1040982 # Number of data accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_misses::realview.ide 8897 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8934 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2016-02-24 10:16:59 +01:00
system.iocache.demand_misses::realview.ide 8897 # number of demand (read+write) misses
system.iocache.demand_misses::total 8937 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2016-02-24 10:16:59 +01:00
system.iocache.overall_misses::realview.ide 8897 # number of overall misses
system.iocache.overall_misses::total 8937 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5248000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1663076066 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1668324066 # number of ReadReq miss cycles
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13545989103 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13545989103 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5617000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1663076066 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1668693066 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5617000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1663076066 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1668693066 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_accesses::realview.ide 8897 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8934 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2016-02-24 10:16:59 +01:00
system.iocache.demand_accesses::realview.ide 8897 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8937 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2016-02-24 10:16:59 +01:00
system.iocache.overall_accesses::realview.ide 8897 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8937 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141837.837838 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 186925.487917 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 186738.758227 # average ReadReq miss latency
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126920.668456 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126920.668456 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 140425 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 186925.487917 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 186717.362202 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 140425 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 186925.487917 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 186717.362202 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 33278 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.696387 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 8897 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8934 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2016-02-24 10:16:59 +01:00
system.iocache.demand_mshr_misses::realview.ide 8897 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8937 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2016-02-24 10:16:59 +01:00
system.iocache.overall_mshr_misses::realview.ide 8897 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8937 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3398000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1218226066 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1221624066 # number of ReadReq MSHR miss cycles
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8203200483 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8203200483 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3617000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1218226066 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1221843066 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3617000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1218226066 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1221843066 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91837.837838 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136925.487917 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 136738.758227 # average ReadReq mshr miss latency
2015-07-30 09:42:27 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76860.809563 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76860.809563 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90425 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90425 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.l2c.tags.replacements 1667118 # number of replacements
system.l2c.tags.tagsinuse 63361.638008 # Cycle average of tags in use
system.l2c.tags.total_refs 6455366 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1727204 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 3.737466 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 4891044000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 22165.641734 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 239.050229 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 385.051566 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4239.404809 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 8813.325361 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14013.639467 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 94.428510 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 121.397759 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2981.044706 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 5621.582558 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4687.071308 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.338221 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003648 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.005875 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.064688 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.134481 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.213831 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001441 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.001852 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.045487 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.085779 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071519 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.966822 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 9996 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 49839 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 1469 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 8111 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
2016-02-24 10:16:59 +01:00
system.l2c.tags.age_task_id_blocks_1023::4 247 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2991 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5625 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 40782 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.152527 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003830 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.760483 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 82621731 # Number of tag accesses
system.l2c.tags.data_accesses 82621731 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 3012753 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 3012753 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 2 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 188217 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 137513 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 325730 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 45011 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 38650 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 83661 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 56653 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 53670 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 110323 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6963 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4319 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 567930 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 682126 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 295320 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6606 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4484 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 500301 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 595581 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 300895 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2964525 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 123921 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 128483 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 252404 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6963 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4319 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 567930 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 738779 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 295320 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 6606 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4484 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 500301 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 649251 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 300895 # number of demand (read+write) hits
system.l2c.demand_hits::total 3074848 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6963 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4319 # number of overall hits
system.l2c.overall_hits::cpu0.inst 567930 # number of overall hits
system.l2c.overall_hits::cpu0.data 738779 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 295320 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 6606 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4484 # number of overall hits
system.l2c.overall_hits::cpu1.inst 500301 # number of overall hits
system.l2c.overall_hits::cpu1.data 649251 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 300895 # number of overall hits
system.l2c.overall_hits::total 3074848 # number of overall hits
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system.l2c.UpgradeReq_misses::cpu1.data 64352 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 128129 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 13748 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 11919 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 25667 # number of SCUpgradeReq misses
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system.l2c.ReadExReq_misses::cpu1.data 50904 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 148166 # number of ReadExReq misses
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system.l2c.ReadSharedReq_misses::cpu0.inst 64884 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 181110 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 386357 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2034 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1570 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 45959 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 114229 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 215943 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 1019541 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 509164 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 100519 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 609683 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 3782 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3673 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 64884 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 278372 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 386357 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2034 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1570 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 45959 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 165133 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 215943 # number of demand (read+write) misses
system.l2c.demand_misses::total 1167707 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 3782 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3673 # number of overall misses
system.l2c.overall_misses::cpu0.inst 64884 # number of overall misses
system.l2c.overall_misses::cpu0.data 278372 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 386357 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2034 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1570 # number of overall misses
system.l2c.overall_misses::cpu1.inst 45959 # number of overall misses
system.l2c.overall_misses::cpu1.data 165133 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 215943 # number of overall misses
system.l2c.overall_misses::total 1167707 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 1085442500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 1077777500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 2163220000 # number of UpgradeReq miss cycles
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system.l2c.SCUpgradeReq_miss_latency::cpu1.data 184474000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 396447500 # number of SCUpgradeReq miss cycles
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system.l2c.ReadExReq_miss_latency::cpu1.data 6989170497 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 20935814991 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 531173000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 521770500 # number of ReadSharedReq miss cycles
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system.l2c.ReadSharedReq_miss_latency::cpu0.data 26625748999 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 72546834291 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 297030000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 228999000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6329750999 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 16747831000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39888708640 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 172665130430 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 156554500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 157821500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 314376000 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 531173000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 521770500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 8947284001 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 40572393493 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 72546834291 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 297030000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 228999000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 6329750999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 23737001497 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39888708640 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 193600945421 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 531173000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 521770500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 8947284001 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu1.dtb.walker 297030000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 228999000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 6329750999 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 23737001497 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39888708640 # number of overall miss cycles
system.l2c.overall_miss_latency::total 193600945421 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 3012753 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 3012753 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 251994 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 201865 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 453859 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 58759 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 50569 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 109328 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 153915 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 104574 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 258489 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10745 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7992 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 632814 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 863236 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 681677 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8640 # number of ReadSharedReq accesses(hits+misses)
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system.l2c.ReadSharedReq_accesses::cpu1.inst 546260 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 709810 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 516838 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 3984066 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 633085 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 229002 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 862087 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 10745 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 7992 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 632814 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1017151 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 681677 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 8640 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6054 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 546260 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 814384 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 516838 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 4242555 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 10745 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 7992 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 632814 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1017151 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 681677 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 8640 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6054 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 546260 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 814384 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 516838 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 4242555 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.253089 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.318787 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.282310 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.233973 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.235698 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.234771 # miss rate for SCUpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::cpu1.data 0.486775 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.573200 # miss rate for ReadExReq accesses
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system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.459585 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102532 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.209804 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.566774 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.235417 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.259333 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.084134 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.160929 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.417816 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.255905 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804259 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.438944 # miss rate for InvalidateReq accesses
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system.l2c.demand_miss_rate::cpu0.inst 0.102532 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.273678 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.566774 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.235417 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.259333 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.084134 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.202770 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.417816 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.275237 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.351978 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.459585 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.102532 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.273678 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.566774 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.235417 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.259333 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.084134 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.202770 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.417816 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.275237 # miss rate for overall accesses
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2014-12-02 12:08:05 +01:00
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2016-02-24 10:16:59 +01:00
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2016-02-24 10:16:59 +01:00
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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2015-11-06 09:26:50 +01:00
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2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
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2016-02-24 10:16:59 +01:00
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system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.438944 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.707217 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.273646 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.202746 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.275132 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.273646 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.202746 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.275132 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70448.531555 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70759.533394 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70604.730311 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73634.273785 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73691.039349 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73660.634044 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 133387.815570 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 127291.827027 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 131293.474083 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137013.813278 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136612.753688 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159370.250555 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70113.311234 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 70257.085725 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70137.015467 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135746.754803 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 133739.131074 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 155806.340709 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135746.754803 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 133739.131074 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 155806.340709 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168235.634593 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139802.229848 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139452.164338 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164282.633343 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145775.972367 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156258.745989 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166168.682074 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142619.113794 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 146010.226499 # average overall mshr uncacheable latency
2014-12-02 12:08:05 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::ReadReq 59609 # Transaction distribution
system.membus.trans_dist::ReadResp 1087641 # Transaction distribution
system.membus.trans_dist::WriteReq 38144 # Transaction distribution
system.membus.trans_dist::WriteResp 38144 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1427135 # Transaction distribution
system.membus.trans_dist::CleanEvict 277667 # Transaction distribution
system.membus.trans_dist::UpgradeReq 445891 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 321137 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 156981 # Transaction distribution
system.membus.trans_dist::ReadExResp 142959 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1028032 # Transaction distribution
system.membus.trans_dist::InvalidateReq 712467 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122696 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24870 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5347246 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 5494888 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237811 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237811 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5732699 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155826 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49740 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159196224 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 159402346 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7246976 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7246976 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 166649322 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 621233 # Total snoops (count)
system.membus.snoop_fanout::samples 4467120 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::1 4467120 100.00% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::total 4467120 # Request fanout histogram
system.membus.reqLayer0.occupancy 98530997 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.reqLayer2.occupancy 20867984 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.reqLayer5.occupancy 9912231208 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.respLayer2.occupancy 6259994034 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.respLayer3.occupancy 45597361 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-12-02 12:08:05 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoop_filter.tot_requests 12663754 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6874752 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 2026071 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 169438 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 153466 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 15972 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 59611 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4844529 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38144 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38144 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 4439938 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2880952 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 762470 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 404798 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1167268 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 311901 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 311901 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4792157 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 968815 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 862087 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10699681 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7828066 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 18527747 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 272166853 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 192849765 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 465016618 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 3356905 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 9121086 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.343228 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.478461 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoop_fanout::0 6006442 65.85% 65.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3098672 33.97% 99.82% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 15972 0.18% 100.00% # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoop_fanout::total 9121086 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 9875342461 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoopLayer0.occupancy 2628126 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer0.occupancy 4863215068 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer1.occupancy 3891669395 # Layer occupancy (ticks)
2014-12-02 12:08:05 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-02-24 10:16:59 +01:00
system.cpu0.kern.inst.quiesce 5261 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-02-24 10:16:59 +01:00
system.cpu1.kern.inst.quiesce 13576 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
