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Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
# -*- mode:python -*-
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Updated Authors from bk prs info --HG-- extra : convert_revision : 77f475b156d81c03a2811818fa23593d5615c685
2006-06-01 01:26:56 +02:00
#
# Authors: Steve Reinhardt
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. --HG-- extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-11 08:00:54 +01:00
Import('*')
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
SCons: Support building without an ISA
2010-11-20 01:00:39 +01:00
if env['TARGET_ISA'] == 'no':
Return()
Make sure cpu/static_inst_exec_sigs.hh get rebuilt when CPU_MODELS parameter changes. arch/SConscript: Fix typo in comment. cpu/SConscript: Convert exec signature generator to Action so we can add dependency on CPU_MODELS environment var. Print nicer string while we're at it. Also add some comments. --HG-- extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
2006-02-26 04:57:46 +01:00
#################################################################
#
# Generate StaticInst execute() method signatures.
#
# There must be one signature for each CPU model compiled in.
# Since the set of compiled-in models is flexible, we generate a
# header containing the appropriate set of signatures on the fly.
#
#################################################################
# Template for execute() signature.
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
exec_sig_template = '''
CPU: Prepare CPU models for the new in-order CPU model. Some new functions and forward declarations are necessary to make things work
2009-02-11 00:49:29 +01:00
virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
inorder/alpha-isa: create eaComp object visible to StaticInst through ISA Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *
2009-05-12 21:01:14 +02:00
virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
CPU: Prepare CPU models for the new in-order CPU model. Some new functions and forward declarations are necessary to make things work
2009-02-11 00:49:29 +01:00
virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-27 00:48:51 +01:00
{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
CPU: Prepare CPU models for the new in-order CPU model. Some new functions and forward declarations are necessary to make things work
2009-02-11 00:49:29 +01:00
virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
Split SimpleCPU into two different models, AtomicSimpleCPU and TimingSimpleCPU, which use atomic and timing memory accesses respectively. Common code is factored into the BaseSimpleCPU class. AtomicSimpleCPU includes an option (simulate_stalls) to add delays based on the estimated latency reported by the atomic accesses. Plain old "SimpleCPU" is gone; I have not updated all the config files (just test/test.py). Also fixes to get timing accesses working in new memory model and to get split-phase memory instruction definitions working with new memory model as well. arch/alpha/isa/main.isa: Need to include packet_impl.h for functions that use Packet objects. arch/alpha/isa/mem.isa: Change completeAcc() methods to take Packet object pointers. Also split out StoreCond template for completeAcc(), since that's the only one that needs write_result and we get an unused variable warning if we always have it in there. build/SConstruct: Update list of recognized CPU model names. configs/test/test.py: Change SimpleCPU to AtomicSimpleCPU. cpu/SConscript: Define sources for new CPU models. Add split memory access methods to CPU model signatures. cpu/cpu_models.py: cpu/static_inst.hh: Define new CPU models. cpu/simple/base.cc: cpu/simple/base.hh: Factor out pieces specific to Atomic or Timing models. mem/bus.cc: Bus needs to be able to route timing packets based on explicit dest so responses can get back to requester. Set dest to Packet::Broadcast to indicate that dest should be derived from address. Also set packet src field based on port from which packet is sent. mem/bus.hh: Set packet src field based on port from which packet is sent. mem/packet.hh: Define Broadcast destination address to indicate that packet should be routed based on address. mem/physical.cc: Set packet dest on response so packet is routed back to requester properly. mem/port.cc: Flag blob packets as Broadcast. python/m5/objects/PhysicalMemory.py: Change default latency to be 1 cycle. --HG-- rename : cpu/simple/cpu.cc => cpu/simple/base.cc rename : cpu/simple/cpu.hh => cpu/simple/base.hh extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
2006-05-16 23:36:50 +02:00
Trace::InstRecord *traceData) const
make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-27 00:48:51 +01:00
{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
'''
Updates for O3 model. arch/alpha/isa/decoder.isa: Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model. arch/alpha/isa/pal.isa: Allow IPR instructions to have flags. base/traceflags.py: Include new trace flags from the two new CPU models. cpu/SConscript: Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next). cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Update to the BaseDynInst for the new models. --HG-- extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
2006-04-23 00:26:48 +02:00
mem_ini_sig_template = '''
inorder/alpha-isa: create eaComp object visible to StaticInst through ISA Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *
2009-05-12 21:01:14 +02:00
virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-27 00:48:51 +01:00
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
Updates for O3 model. arch/alpha/isa/decoder.isa: Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model. arch/alpha/isa/pal.isa: Allow IPR instructions to have flags. base/traceflags.py: Include new trace flags from the two new CPU models. cpu/SConscript: Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next). cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Update to the BaseDynInst for the new models. --HG-- extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
2006-04-23 00:26:48 +02:00
'''
mem_comp_sig_template = '''
make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-27 00:48:51 +01:00
virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
Updates for O3 model. arch/alpha/isa/decoder.isa: Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model. arch/alpha/isa/pal.isa: Allow IPR instructions to have flags. base/traceflags.py: Include new trace flags from the two new CPU models. cpu/SConscript: Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next). cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Update to the BaseDynInst for the new models. --HG-- extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
2006-04-23 00:26:48 +02:00
'''
Fix up code to be able to use the Checker. SConstruct: Remove check for Checker from this SConstruct src/arch/SConscript: Specific check if CheckerCPU is being used. Not the cleanest, but works for now. src/cpu/SConscript: Code to handle using the CheckerCPU a little better. Allows -c to be used normally. --HG-- extra : convert_revision : 0a82f16db0f38e5ce114d08368477bd211331fa3
2006-06-18 04:01:30 +02:00
# Generate a temporary CPU list, including the CheckerCPU if
# it's enabled. This isn't used for anything else other than StaticInst
# headers.
Fix the CheckerCPU being included via python. src/arch/SConscript: Fixes for including the CheckerCPU if it's specified via command line. Previously the env variable was actually being modified. src/cpu/SConscript: Copy the CPU_MODELS from the env, don't create a proxy to it. --HG-- extra : convert_revision : 7d069bd93a6834ccaa1c378b2bc76dce76745c19
2006-07-14 23:51:29 +02:00
temp_cpu_list = env['CPU_MODELS'][:]
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
2012-03-09 15:59:27 +01:00
temp_cpu_list.append('CheckerCPU')
SimObject('CheckerCPU.py')
Fix up code to be able to use the Checker. SConstruct: Remove check for Checker from this SConstruct src/arch/SConscript: Specific check if CheckerCPU is being used. Not the cleanest, but works for now. src/cpu/SConscript: Code to handle using the CheckerCPU a little better. Allows -c to be used normally. --HG-- extra : convert_revision : 0a82f16db0f38e5ce114d08368477bd211331fa3
2006-06-18 04:01:30 +02:00
Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-24 06:51:38 +02:00
# Generate header.
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
def gen_cpu_exec_signatures(target, source, env):
f = open(str(target[0]), 'w')
print >> f, '''
#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
#define __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
Fix up code to be able to use the Checker. SConstruct: Remove check for Checker from this SConstruct src/arch/SConscript: Specific check if CheckerCPU is being used. Not the cleanest, but works for now. src/cpu/SConscript: Code to handle using the CheckerCPU a little better. Allows -c to be used normally. --HG-- extra : convert_revision : 0a82f16db0f38e5ce114d08368477bd211331fa3
2006-06-18 04:01:30 +02:00
for cpu in temp_cpu_list:
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
CPU: Prepare CPU models for the new in-order CPU model. Some new functions and forward declarations are necessary to make things work
2009-02-11 00:49:29 +01:00
print >> f, exec_sig_template % { 'type' : xc_type }
Enable building only selected CPU models via new scons CPU_MODELS parameter. For example: scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug Unfortunately the option is not sticky due to a scons bug with saving & restoring ListOption parameters. SConscript: Separate out cpu-model-specific files so they can be conditionally included based on value of new CPU_MODELS parameter. Most of these are now handled in cpu/SConscript, except for FullCPU which is still in this file. arch/SConscript: The set of CPU-model-specific execute files must now be determined from the CPU_MODELS parameter, via the new cpu_models.py file. Also pass the list of configured CPU models to isa_parser.py. arch/isa_parser.py: Move CpuModel definition and objects out to a separate file so they can be shared with scons. Global list of CPU models to generate code for is now controlled by command-line parameters (so we can do only a subset of the available ones). build/SConstruct: Define new CPU_MODELS ListOption. cpu/static_inst.hh: Rename static_inst_impl.hh to static_inst_exec_sigs.hh. --HG-- extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 23:00:29 +01:00
print >> f, '''
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
Make sure cpu/static_inst_exec_sigs.hh get rebuilt when CPU_MODELS parameter changes. arch/SConscript: Fix typo in comment. cpu/SConscript: Convert exec signature generator to Action so we can add dependency on CPU_MODELS environment var. Print nicer string while we're at it. Also add some comments. --HG-- extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
2006-02-26 04:57:46 +01:00
# Generate string that gets printed when header is rebuilt
def gen_sigs_string(target, source, env):
SCons: Cleanup SCons output during compile
2010-11-15 21:04:04 +01:00
return " [GENERATE] static_inst_exec_sigs.hh: " \
Fix up code to be able to use the Checker. SConstruct: Remove check for Checker from this SConstruct src/arch/SConscript: Specific check if CheckerCPU is being used. Not the cleanest, but works for now. src/cpu/SConscript: Code to handle using the CheckerCPU a little better. Allows -c to be used normally. --HG-- extra : convert_revision : 0a82f16db0f38e5ce114d08368477bd211331fa3
2006-06-18 04:01:30 +02:00
+ ', '.join(temp_cpu_list)
Make sure cpu/static_inst_exec_sigs.hh get rebuilt when CPU_MODELS parameter changes. arch/SConscript: Fix typo in comment. cpu/SConscript: Convert exec signature generator to Action so we can add dependency on CPU_MODELS environment var. Print nicer string while we're at it. Also add some comments. --HG-- extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
2006-02-26 04:57:46 +01:00
# Add command to generate header to environment.
cpu_models: get rid of cpu_models.py and move the stuff into SCons
2010-02-27 03:14:48 +01:00
env.Command('static_inst_exec_sigs.hh', (),
Make sure cpu/static_inst_exec_sigs.hh get rebuilt when CPU_MODELS parameter changes. arch/SConscript: Fix typo in comment. cpu/SConscript: Convert exec signature generator to Action so we can add dependency on CPU_MODELS environment var. Print nicer string while we're at it. Also add some comments. --HG-- extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
2006-02-26 04:57:46 +01:00
Action(gen_cpu_exec_signatures, gen_sigs_string,
Fix up code to be able to use the Checker. SConstruct: Remove check for Checker from this SConstruct src/arch/SConscript: Specific check if CheckerCPU is being used. Not the cleanest, but works for now. src/cpu/SConscript: Code to handle using the CheckerCPU a little better. Allows -c to be used normally. --HG-- extra : convert_revision : 0a82f16db0f38e5ce114d08368477bd211331fa3
2006-06-18 04:01:30 +02:00
varlist = temp_cpu_list))
Fix to have the static inst exec sigs also dependent on the CPU models used. --HG-- extra : convert_revision : 65d978d638dd9a57a641ca52adcf2c0ef48edf1c
2006-06-23 00:03:08 +02:00
env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
Make sure cpu/static_inst_exec_sigs.hh get rebuilt when CPU_MODELS parameter changes. arch/SConscript: Fix typo in comment. cpu/SConscript: Convert exec signature generator to Action so we can add dependency on CPU_MODELS environment var. Print nicer string while we're at it. Also add some comments. --HG-- extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
2006-02-26 04:57:46 +01:00
Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-28 04:21:17 +02:00
SimObject('BaseCPU.py')
SimObject('FuncUnit.py')
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
SE/FS: Build the devices in SE mode.
2011-09-30 09:28:33 +02:00
SimObject('IntrControl.py')
CPU: Separate out native trace into ISA (in)dependent code and SimObjects. --HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-20 08:54:56 +02:00
SimObject('NativeTrace.py')
Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-28 04:21:17 +02:00
Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. --HG-- extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-11 08:00:54 +01:00
Source('activity.cc')
Source('base.cc')
Source('cpuevent.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
Source('inteltrace.cc')
SE/FS: Build the devices in SE mode.
2011-09-30 09:28:33 +02:00
Source('intr_control.cc')
CPU: Separate out native trace into ISA (in)dependent code and SimObjects. --HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-20 08:54:56 +02:00
Source('nativetrace.cc')
Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. --HG-- extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-11 08:00:54 +01:00
Source('pc_event.cc')
SE/FS: Make the functions available from the TC consistent between SE and FS.
2011-10-31 10:58:22 +01:00
Source('profile.cc')
Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. --HG-- extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-11 08:00:54 +01:00
Source('quiesce_event.cc')
Source('static_inst.cc')
Source('simple_thread.cc')
CPU: Add function to explictly compare thread contexts after copying. --HG-- extra : convert_revision : 9b7af59a11202a91409aad7c427b7749cd1d2f12
2007-11-08 16:46:41 +01:00
Source('thread_context.cc')
Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. --HG-- extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-11 08:00:54 +01:00
Source('thread_state.cc')
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
2011-11-18 10:33:28 +01:00
if env['TARGET_ISA'] == 'sparc':
SimObject('LegionTrace.py')
Source('legiontrace.cc')
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
2012-03-09 15:59:27 +01:00
SimObject('DummyChecker.py')
Source('checker/cpu.cc')
cpu: Add header files for checker CPUs In order to create reliable SWIG wrappers, we need to include the declaration of the wrapped class in the SWIG file. Previously, we didn't expose the declaration of checker CPUs. This patch adds header files for such CPUs and include them in the SWIG wrapper. --HG-- rename : src/cpu/dummy_checker_builder.cc => src/cpu/dummy_checker.cc rename : src/cpu/o3/checker_builder.cc => src/cpu/o3/checker.cc
2012-11-02 17:32:01 +01:00
Source('dummy_checker.cc')
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
2012-03-09 15:59:27 +01:00
DebugFlag('Checker')
Traceflags: Add SCons function to created a traceflag instead of having one file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-31 06:21:54 +01:00
scons: rename TraceFlags to DebugFlags
2011-06-03 02:36:21 +02:00
DebugFlag('Activity')
DebugFlag('Commit')
DebugFlag('Context')
DebugFlag('Decode')
DebugFlag('DynInst')
DebugFlag('ExecEnable')
DebugFlag('ExecCPSeq')
DebugFlag('ExecEffAddr')
DebugFlag('ExecFaulting', 'Trace faulting instructions')
DebugFlag('ExecFetchSeq')
DebugFlag('ExecOpClass')
DebugFlag('ExecRegDelta')
DebugFlag('ExecResult')
DebugFlag('ExecSpeculative')
DebugFlag('ExecSymbol')
DebugFlag('ExecThread')
DebugFlag('ExecTicks')
DebugFlag('ExecMicro')
DebugFlag('ExecMacro')
DebugFlag('ExecUser')
DebugFlag('ExecKernel')
DebugFlag('ExecAsid')
DebugFlag('Fetch')
DebugFlag('IntrControl')
O3: Create a pipeline activity viewer for the O3 CPU model. Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py) and modified O3 code base to support an extra trace flag (O3PipeView) for generating traces to be used as inputs by the tool.
2011-07-15 18:53:35 +02:00
DebugFlag('O3PipeView')
scons: rename TraceFlags to DebugFlags
2011-06-03 02:36:21 +02:00
DebugFlag('PCEvent')
DebugFlag('Quiesce')
Traceflags: Add SCons function to created a traceflag instead of having one file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-31 06:21:54 +01:00
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15 19:44:32 +02:00
CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and ExecKernel are set by default when Exec is specified. Use minus sign with ExecUser or ExecKernel to remove user or kernel tracing respectively.
2011-05-14 00:27:00 +02:00
'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
'ExecAsid' ])
Traceflags: Add SCons function to created a traceflag instead of having one file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-31 06:21:54 +01:00
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and ExecKernel are set by default when Exec is specified. Use minus sign with ExecUser or ExecKernel to remove user or kernel tracing respectively.
2011-05-14 00:27:00 +02:00
'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
'ExecUser', 'ExecKernel' ])
o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly
2009-04-18 16:42:29 +02:00
CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and ExecKernel are set by default when Exec is specified. Use minus sign with ExecUser or ExecKernel to remove user or kernel tracing respectively.
2011-05-14 00:27:00 +02:00
'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
'ExecUser', 'ExecKernel' ])
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