2012-01-17 19:55:08 +01:00
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# Copyright (c) 2010-2012 ARM Limited
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2010-08-23 18:18:40 +02:00
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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2011-02-07 07:14:18 +01:00
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# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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2008-01-12 12:39:15 +01:00
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# Copyright (c) 2006-2008 The Regents of The University of Michigan
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2006-07-21 21:56:35 +02:00
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Kevin Lim
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from m5.objects import *
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2006-08-16 01:12:19 +02:00
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from Benchmarks import *
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2011-08-19 22:08:09 +02:00
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from m5.util import convert
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2006-07-21 21:56:35 +02:00
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class CowIdeDisk(IdeDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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class MemBus(CoherentBus):
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2008-07-16 20:10:33 +02:00
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badaddr_responder = BadAddr()
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default = Self.badaddr_responder.pio
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2013-08-19 09:52:27 +02:00
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def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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2012-01-17 19:55:09 +01:00
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IO_address_space_base = 0x80000000000
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2007-06-04 18:03:38 +02:00
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class BaseTsunami(Tsunami):
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2007-08-16 22:49:05 +02:00
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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2007-06-04 18:03:38 +02:00
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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2006-07-21 21:56:35 +02:00
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self = LinuxAlphaSystem()
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2006-08-16 20:42:44 +02:00
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if not mdesc:
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# generic system
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2006-10-17 20:08:49 +02:00
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mdesc = SysConfig()
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2006-08-16 01:12:19 +02:00
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self.readfile = mdesc.script()
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Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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self.iobus = NoncoherentBus()
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self.membus = MemBus()
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2012-01-17 19:55:09 +01:00
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# By default the bridge responds to all addresses above the I/O
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# base address (including the PCI config space)
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Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.
The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).
As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 17:39:58 +02:00
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self.bridge = Bridge(delay='50ns',
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2012-01-17 19:55:09 +01:00
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ranges = [AddrRange(IO_address_space_base, Addr.max)])
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2013-08-19 09:52:27 +02:00
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self.mem_ranges = [AddrRange(mdesc.mem())]
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2012-02-13 12:43:09 +01:00
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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2006-07-21 21:56:35 +02:00
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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2006-08-16 01:12:19 +02:00
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self.disk0.childImage(mdesc.disk())
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2006-07-21 21:56:35 +02:00
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.tsunami = BaseTsunami()
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self.tsunami.attachIO(self.iobus)
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2012-02-13 12:43:09 +01:00
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self.tsunami.ide.pio = self.iobus.master
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self.tsunami.ide.config = self.iobus.master
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self.tsunami.ide.dma = self.iobus.slave
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self.tsunami.ethernet.pio = self.iobus.master
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self.tsunami.ethernet.config = self.iobus.master
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self.tsunami.ethernet.dma = self.iobus.slave
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2009-11-18 22:55:58 +01:00
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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self.mem_mode = mem_mode
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self.terminal = Terminal()
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self.kernel = binary('vmlinux')
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self.pal = binary('ts_osfpal')
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self.console = binary('console')
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self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
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2012-02-13 12:43:09 +01:00
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self.system_port = self.membus.slave
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2012-01-17 19:55:08 +01:00
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2009-11-18 22:55:58 +01:00
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return self
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2013-08-19 09:52:27 +02:00
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def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
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2009-11-18 22:55:58 +01:00
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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2013-08-19 09:52:27 +02:00
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self = LinuxAlphaSystem()
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self.mem_ranges = [AddrRange(mdesc.mem())]
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2009-11-18 22:55:58 +01:00
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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# Create pio bus to connect all device pio ports to rubymem's pio port
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Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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self.piobus = NoncoherentBus()
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2010-01-30 05:29:21 +01:00
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2009-11-18 22:55:58 +01:00
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.tsunami = BaseTsunami()
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self.tsunami.attachIO(self.piobus)
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2012-02-13 12:43:09 +01:00
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self.tsunami.ide.pio = self.piobus.master
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self.tsunami.ide.config = self.piobus.master
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self.tsunami.ethernet.pio = self.piobus.master
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self.tsunami.ethernet.config = self.piobus.master
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2009-11-18 22:55:58 +01:00
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2010-01-30 05:29:21 +01:00
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#
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2010-08-24 22:20:31 +02:00
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# Store the dma devices for later connection to dma ruby ports.
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# Append an underscore to dma_devices to avoid the SimObjectVector check.
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2010-01-30 05:29:21 +01:00
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#
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2012-04-05 18:09:19 +02:00
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self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
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2009-11-18 22:55:58 +01:00
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2006-08-16 01:12:19 +02:00
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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2006-07-21 21:56:35 +02:00
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read_only = True))
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self.intrctrl = IntrControl()
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2006-07-22 21:50:39 +02:00
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self.mem_mode = mem_mode
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2008-06-18 05:29:06 +02:00
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self.terminal = Terminal()
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2006-07-21 21:56:35 +02:00
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self.kernel = binary('vmlinux')
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2006-10-30 22:55:52 +01:00
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self.pal = binary('ts_osfpal')
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2006-07-21 21:56:35 +02:00
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self.console = binary('console')
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self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
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return self
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2013-08-19 09:52:27 +02:00
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def makeSparcSystem(mem_mode, mdesc = None):
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2012-01-17 19:55:09 +01:00
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# Constants from iob.cc and uart8250.cc
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iob_man_addr = 0x9800000000
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uart_pio_size = 8
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2007-05-28 04:21:17 +02:00
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class CowMmDisk(MmDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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2006-11-10 00:22:46 +01:00
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self = SparcSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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self.iobus = NoncoherentBus()
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self.membus = MemBus()
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Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.
The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).
As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 17:39:58 +02:00
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self.bridge = Bridge(delay='50ns')
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2006-11-16 18:34:10 +01:00
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self.t1000 = T1000()
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2007-03-04 01:02:31 +01:00
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self.t1000.attachOnChipIO(self.membus)
|
2006-11-16 18:34:10 +01:00
|
|
|
self.t1000.attachIO(self.iobus)
|
2013-08-19 09:52:27 +02:00
|
|
|
self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
|
|
|
|
|
AddrRange(Addr('2GB'), size ='256MB')]
|
2012-02-13 12:43:09 +01:00
|
|
|
self.bridge.master = self.iobus.slave
|
|
|
|
|
self.bridge.slave = self.membus.master
|
|
|
|
|
self.rom.port = self.membus.master
|
|
|
|
|
self.nvram.port = self.membus.master
|
|
|
|
|
self.hypervisor_desc.port = self.membus.master
|
|
|
|
|
self.partition_desc.port = self.membus.master
|
2006-11-10 00:22:46 +01:00
|
|
|
self.intrctrl = IntrControl()
|
2007-01-10 04:16:49 +01:00
|
|
|
self.disk0 = CowMmDisk()
|
|
|
|
|
self.disk0.childImage(disk('disk.s10hw2'))
|
2012-02-13 12:43:09 +01:00
|
|
|
self.disk0.pio = self.iobus.master
|
2012-01-17 19:55:09 +01:00
|
|
|
|
|
|
|
|
# The puart0 and hvuart are placed on the IO bus, so create ranges
|
|
|
|
|
# for them. The remaining IO range is rather fragmented, so poke
|
|
|
|
|
# holes for the iob and partition descriptors etc.
|
|
|
|
|
self.bridge.ranges = \
|
|
|
|
|
[
|
|
|
|
|
AddrRange(self.t1000.puart0.pio_addr,
|
|
|
|
|
self.t1000.puart0.pio_addr + uart_pio_size - 1),
|
|
|
|
|
AddrRange(self.disk0.pio_addr,
|
|
|
|
|
self.t1000.fake_jbi.pio_addr +
|
|
|
|
|
self.t1000.fake_jbi.pio_size - 1),
|
|
|
|
|
AddrRange(self.t1000.fake_clk.pio_addr,
|
|
|
|
|
iob_man_addr - 1),
|
|
|
|
|
AddrRange(self.t1000.fake_l2_1.pio_addr,
|
|
|
|
|
self.t1000.fake_ssi.pio_addr +
|
|
|
|
|
self.t1000.fake_ssi.pio_size - 1),
|
|
|
|
|
AddrRange(self.t1000.hvuart.pio_addr,
|
|
|
|
|
self.t1000.hvuart.pio_addr + uart_pio_size - 1)
|
|
|
|
|
]
|
2007-03-03 23:22:47 +01:00
|
|
|
self.reset_bin = binary('reset_new.bin')
|
|
|
|
|
self.hypervisor_bin = binary('q_new.bin')
|
|
|
|
|
self.openboot_bin = binary('openboot_new.bin')
|
2006-11-20 23:59:35 +01:00
|
|
|
self.nvram_bin = binary('nvram1')
|
|
|
|
|
self.hypervisor_desc_bin = binary('1up-hv.bin')
|
|
|
|
|
self.partition_desc_bin = binary('1up-md.bin')
|
2006-11-10 00:22:46 +01:00
|
|
|
|
2012-02-13 12:43:09 +01:00
|
|
|
self.system_port = self.membus.slave
|
2012-01-17 19:55:08 +01:00
|
|
|
|
2006-11-10 00:22:46 +01:00
|
|
|
return self
|
|
|
|
|
|
2013-08-19 09:52:27 +02:00
|
|
|
def makeArmSystem(mem_mode, machine_type, mdesc = None,
|
2013-04-22 19:20:33 +02:00
|
|
|
dtb_filename = None, bare_metal=False):
|
2011-02-23 22:10:48 +01:00
|
|
|
assert machine_type
|
|
|
|
|
|
2010-08-23 18:18:40 +02:00
|
|
|
if bare_metal:
|
|
|
|
|
self = ArmSystem()
|
|
|
|
|
else:
|
|
|
|
|
self = LinuxArmSystem()
|
|
|
|
|
|
|
|
|
|
if not mdesc:
|
|
|
|
|
# generic system
|
|
|
|
|
mdesc = SysConfig()
|
|
|
|
|
|
|
|
|
|
self.readfile = mdesc.script()
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
self.iobus = NoncoherentBus()
|
|
|
|
|
self.membus = MemBus()
|
2010-08-23 18:18:40 +02:00
|
|
|
self.membus.badaddr_responder.warn_access = "warn"
|
Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.
The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).
As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 17:39:58 +02:00
|
|
|
self.bridge = Bridge(delay='50ns')
|
2012-02-13 12:43:09 +01:00
|
|
|
self.bridge.master = self.iobus.slave
|
|
|
|
|
self.bridge.slave = self.membus.master
|
2010-08-23 18:18:40 +02:00
|
|
|
|
|
|
|
|
self.mem_mode = mem_mode
|
|
|
|
|
|
|
|
|
|
if machine_type == "RealView_PBX":
|
|
|
|
|
self.realview = RealViewPBX()
|
|
|
|
|
elif machine_type == "RealView_EB":
|
|
|
|
|
self.realview = RealViewEB()
|
2011-08-19 22:08:08 +02:00
|
|
|
elif machine_type == "VExpress_ELT":
|
|
|
|
|
self.realview = VExpress_ELT()
|
2012-03-02 00:26:31 +01:00
|
|
|
elif machine_type == "VExpress_EMM":
|
|
|
|
|
self.realview = VExpress_EMM()
|
|
|
|
|
self.load_addr_mask = 0xffffffff
|
2010-08-23 18:18:40 +02:00
|
|
|
else:
|
|
|
|
|
print "Unknown Machine Type"
|
|
|
|
|
sys.exit(1)
|
|
|
|
|
|
2011-08-19 22:08:09 +02:00
|
|
|
self.cf0 = CowIdeDisk(driveID='master')
|
|
|
|
|
self.cf0.childImage(mdesc.disk())
|
|
|
|
|
# default to an IDE controller rather than a CF one
|
|
|
|
|
# assuming we've got one
|
|
|
|
|
try:
|
|
|
|
|
self.realview.ide.disks = [self.cf0]
|
|
|
|
|
except:
|
|
|
|
|
self.realview.cf_ctrl.disks = [self.cf0]
|
|
|
|
|
|
2011-02-23 22:10:48 +01:00
|
|
|
if bare_metal:
|
|
|
|
|
# EOT character on UART will end the simulation
|
2010-08-23 18:18:40 +02:00
|
|
|
self.realview.uart.end_on_eot = True
|
2013-08-26 17:58:06 +02:00
|
|
|
self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
|
|
|
|
|
size = mdesc.mem())]
|
2011-02-23 22:10:48 +01:00
|
|
|
else:
|
2011-08-19 22:08:09 +02:00
|
|
|
self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
|
2013-02-16 00:48:59 +01:00
|
|
|
if dtb_filename is not None:
|
|
|
|
|
self.dtb_filename = dtb_filename
|
2011-04-04 18:42:31 +02:00
|
|
|
self.machine_type = machine_type
|
2012-03-09 22:45:47 +01:00
|
|
|
if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
|
2012-03-02 00:26:31 +01:00
|
|
|
print "The currently selected ARM platforms doesn't support"
|
|
|
|
|
print " the amount of DRAM you've selected. Please try"
|
|
|
|
|
print " another platform"
|
2012-03-09 22:45:47 +01:00
|
|
|
sys.exit(1)
|
2011-08-19 22:08:09 +02:00
|
|
|
|
2011-04-04 18:42:31 +02:00
|
|
|
boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
|
2011-08-19 22:08:09 +02:00
|
|
|
'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
|
2013-08-19 09:52:27 +02:00
|
|
|
self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
|
|
|
|
|
size = mdesc.mem())]
|
2012-03-02 00:26:31 +01:00
|
|
|
self.realview.setupBootLoader(self.membus, self, binary)
|
2011-08-19 22:08:09 +02:00
|
|
|
self.gic_cpu_addr = self.realview.gic.cpu_addr
|
|
|
|
|
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
|
2011-05-05 03:38:28 +02:00
|
|
|
|
2011-12-15 06:43:35 +01:00
|
|
|
if mdesc.disk().lower().count('android'):
|
2011-10-20 01:08:31 +02:00
|
|
|
boot_flags += " init=/init "
|
2011-04-04 18:42:31 +02:00
|
|
|
self.boot_osflags = boot_flags
|
2012-01-17 19:55:09 +01:00
|
|
|
self.realview.attachOnChipIO(self.membus, self.bridge)
|
2010-08-23 18:18:40 +02:00
|
|
|
self.realview.attachIO(self.iobus)
|
|
|
|
|
self.intrctrl = IntrControl()
|
|
|
|
|
self.terminal = Terminal()
|
2011-02-12 01:29:35 +01:00
|
|
|
self.vncserver = VncServer()
|
2010-08-23 18:18:40 +02:00
|
|
|
|
2012-02-13 12:43:09 +01:00
|
|
|
self.system_port = self.membus.slave
|
2012-01-17 19:55:08 +01:00
|
|
|
|
2010-08-23 18:18:40 +02:00
|
|
|
return self
|
|
|
|
|
|
|
|
|
|
|
2013-08-19 09:52:27 +02:00
|
|
|
def makeLinuxMipsSystem(mem_mode, mdesc = None):
|
2007-11-13 22:58:16 +01:00
|
|
|
class BaseMalta(Malta):
|
|
|
|
|
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
|
|
|
|
|
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
|
|
|
|
|
pci_func=0, pci_dev=0, pci_bus=0)
|
|
|
|
|
|
|
|
|
|
self = LinuxMipsSystem()
|
|
|
|
|
if not mdesc:
|
|
|
|
|
# generic system
|
|
|
|
|
mdesc = SysConfig()
|
|
|
|
|
self.readfile = mdesc.script()
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
self.iobus = NoncoherentBus()
|
|
|
|
|
self.membus = MemBus()
|
Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.
The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).
As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 17:39:58 +02:00
|
|
|
self.bridge = Bridge(delay='50ns')
|
2013-08-19 09:52:27 +02:00
|
|
|
self.mem_ranges = [AddrRange('1GB')]
|
2012-02-13 12:43:09 +01:00
|
|
|
self.bridge.master = self.iobus.slave
|
|
|
|
|
self.bridge.slave = self.membus.master
|
2007-11-13 22:58:16 +01:00
|
|
|
self.disk0 = CowIdeDisk(driveID='master')
|
|
|
|
|
self.disk2 = CowIdeDisk(driveID='master')
|
|
|
|
|
self.disk0.childImage(mdesc.disk())
|
|
|
|
|
self.disk2.childImage(disk('linux-bigswap2.img'))
|
|
|
|
|
self.malta = BaseMalta()
|
|
|
|
|
self.malta.attachIO(self.iobus)
|
2012-02-13 12:43:09 +01:00
|
|
|
self.malta.ide.pio = self.iobus.master
|
|
|
|
|
self.malta.ide.config = self.iobus.master
|
|
|
|
|
self.malta.ide.dma = self.iobus.slave
|
|
|
|
|
self.malta.ethernet.pio = self.iobus.master
|
|
|
|
|
self.malta.ethernet.config = self.iobus.master
|
|
|
|
|
self.malta.ethernet.dma = self.iobus.slave
|
2007-11-13 22:58:16 +01:00
|
|
|
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
|
|
|
|
|
read_only = True))
|
|
|
|
|
self.intrctrl = IntrControl()
|
|
|
|
|
self.mem_mode = mem_mode
|
2008-06-18 05:29:06 +02:00
|
|
|
self.terminal = Terminal()
|
2007-11-13 22:58:16 +01:00
|
|
|
self.kernel = binary('mips/vmlinux')
|
|
|
|
|
self.console = binary('mips/console')
|
|
|
|
|
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
|
|
|
|
|
|
2012-02-13 12:43:09 +01:00
|
|
|
self.system_port = self.membus.slave
|
2012-01-17 19:55:08 +01:00
|
|
|
|
2007-11-13 22:58:16 +01:00
|
|
|
return self
|
|
|
|
|
|
2008-01-12 12:39:15 +01:00
|
|
|
def x86IOAddress(port):
|
2008-02-27 05:38:01 +01:00
|
|
|
IO_address_space_base = 0x8000000000000000
|
2011-05-23 23:29:23 +02:00
|
|
|
return IO_address_space_base + port
|
2008-01-12 12:39:15 +01:00
|
|
|
|
2012-02-27 00:33:07 +01:00
|
|
|
def connectX86ClassicSystem(x86_sys, numCPUs):
|
2012-01-17 19:55:09 +01:00
|
|
|
# Constants similar to x86_traits.hh
|
|
|
|
|
IO_address_space_base = 0x8000000000000000
|
|
|
|
|
pci_config_address_space_base = 0xc000000000000000
|
|
|
|
|
interrupts_address_space_base = 0xa000000000000000
|
|
|
|
|
APIC_range_size = 1 << 12;
|
|
|
|
|
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
x86_sys.membus = MemBus()
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
|
|
|
# North Bridge
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
x86_sys.iobus = NoncoherentBus()
|
Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.
The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).
As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 17:39:58 +02:00
|
|
|
x86_sys.bridge = Bridge(delay='50ns')
|
2012-02-13 12:43:09 +01:00
|
|
|
x86_sys.bridge.master = x86_sys.iobus.slave
|
|
|
|
|
x86_sys.bridge.slave = x86_sys.membus.master
|
2012-01-17 19:55:09 +01:00
|
|
|
# Allow the bridge to pass through the IO APIC (two pages),
|
|
|
|
|
# everything in the IO address range up to the local APIC, and
|
|
|
|
|
# then the entire PCI address space and beyond
|
|
|
|
|
x86_sys.bridge.ranges = \
|
|
|
|
|
[
|
|
|
|
|
AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
|
|
|
|
|
x86_sys.pc.south_bridge.io_apic.pio_addr +
|
|
|
|
|
APIC_range_size - 1),
|
|
|
|
|
AddrRange(IO_address_space_base,
|
|
|
|
|
interrupts_address_space_base - 1),
|
|
|
|
|
AddrRange(pci_config_address_space_base,
|
|
|
|
|
Addr.max)
|
|
|
|
|
]
|
|
|
|
|
|
|
|
|
|
# Create a bridge from the IO bus to the memory bus to allow access to
|
|
|
|
|
# the local APIC (two pages)
|
Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.
The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).
As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 17:39:58 +02:00
|
|
|
x86_sys.apicbridge = Bridge(delay='50ns')
|
2012-02-13 12:43:09 +01:00
|
|
|
x86_sys.apicbridge.slave = x86_sys.iobus.master
|
|
|
|
|
x86_sys.apicbridge.master = x86_sys.membus.slave
|
2012-02-05 10:37:40 +01:00
|
|
|
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
|
|
|
|
|
interrupts_address_space_base +
|
2012-02-27 00:33:07 +01:00
|
|
|
numCPUs * APIC_range_size
|
|
|
|
|
- 1)]
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
|
|
|
# connect the io bus
|
|
|
|
|
x86_sys.pc.attachIO(x86_sys.iobus)
|
|
|
|
|
|
2012-02-13 12:43:09 +01:00
|
|
|
x86_sys.system_port = x86_sys.membus.slave
|
2012-01-17 19:55:08 +01:00
|
|
|
|
2011-02-07 07:14:18 +01:00
|
|
|
def connectX86RubySystem(x86_sys):
|
|
|
|
|
# North Bridge
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
x86_sys.piobus = NoncoherentBus()
|
2011-02-07 07:14:18 +01:00
|
|
|
|
2012-04-05 18:09:19 +02:00
|
|
|
# add the ide to the list of dma devices that later need to attach to
|
|
|
|
|
# dma controllers
|
|
|
|
|
x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
|
|
|
|
|
x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
|
|
|
|
2013-08-19 09:52:27 +02:00
|
|
|
def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
|
2013-04-22 19:20:33 +02:00
|
|
|
Ruby = False):
|
2008-10-10 12:50:30 +02:00
|
|
|
if self == None:
|
|
|
|
|
self = X86System()
|
|
|
|
|
|
2007-10-08 02:52:36 +02:00
|
|
|
if not mdesc:
|
|
|
|
|
# generic system
|
|
|
|
|
mdesc = SysConfig()
|
|
|
|
|
self.readfile = mdesc.script()
|
|
|
|
|
|
2009-12-19 10:49:34 +01:00
|
|
|
self.mem_mode = mem_mode
|
|
|
|
|
|
2007-10-08 02:52:36 +02:00
|
|
|
# Physical memory
|
2013-08-19 09:52:27 +02:00
|
|
|
self.mem_ranges = [AddrRange(mdesc.mem())]
|
2008-10-10 12:50:30 +02:00
|
|
|
|
|
|
|
|
# Platform
|
2008-10-11 11:23:40 +02:00
|
|
|
self.pc = Pc()
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
|
|
|
# Create and connect the busses required by each memory system
|
|
|
|
|
if Ruby:
|
|
|
|
|
connectX86RubySystem(self)
|
|
|
|
|
else:
|
2012-02-27 00:33:07 +01:00
|
|
|
connectX86ClassicSystem(self, numCPUs)
|
2008-10-10 12:50:30 +02:00
|
|
|
|
|
|
|
|
self.intrctrl = IntrControl()
|
|
|
|
|
|
2009-02-01 09:24:26 +01:00
|
|
|
# Disks
|
|
|
|
|
disk0 = CowIdeDisk(driveID='master')
|
|
|
|
|
disk2 = CowIdeDisk(driveID='master')
|
|
|
|
|
disk0.childImage(mdesc.disk())
|
|
|
|
|
disk2.childImage(disk('linux-bigswap2.img'))
|
|
|
|
|
self.pc.south_bridge.ide.disks = [disk0, disk2]
|
|
|
|
|
|
2008-10-10 12:50:51 +02:00
|
|
|
# Add in a Bios information structure.
|
|
|
|
|
structures = [X86SMBiosBiosInformation()]
|
|
|
|
|
self.smbios_table.structures = structures
|
|
|
|
|
|
2008-10-12 00:14:37 +02:00
|
|
|
# Set up the Intel MP table
|
2011-05-23 23:29:23 +02:00
|
|
|
base_entries = []
|
|
|
|
|
ext_entries = []
|
2009-04-26 11:04:32 +02:00
|
|
|
for i in xrange(numCPUs):
|
|
|
|
|
bp = X86IntelMPProcessor(
|
|
|
|
|
local_apic_id = i,
|
|
|
|
|
local_apic_version = 0x14,
|
|
|
|
|
enable = True,
|
|
|
|
|
bootstrap = (i == 0))
|
2011-05-23 23:29:23 +02:00
|
|
|
base_entries.append(bp)
|
2008-10-12 01:12:34 +02:00
|
|
|
io_apic = X86IntelMPIOAPIC(
|
2009-04-26 11:04:32 +02:00
|
|
|
id = numCPUs,
|
2008-10-12 01:12:34 +02:00
|
|
|
version = 0x11,
|
|
|
|
|
enable = True,
|
|
|
|
|
address = 0xfec00000)
|
2009-04-26 11:04:32 +02:00
|
|
|
self.pc.south_bridge.io_apic.apic_id = io_apic.id
|
2011-05-23 23:29:23 +02:00
|
|
|
base_entries.append(io_apic)
|
2008-10-12 01:12:34 +02:00
|
|
|
isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
|
2011-05-23 23:29:23 +02:00
|
|
|
base_entries.append(isa_bus)
|
2009-02-01 09:26:10 +01:00
|
|
|
pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
|
2011-05-23 23:29:23 +02:00
|
|
|
base_entries.append(pci_bus)
|
2009-02-01 09:26:10 +01:00
|
|
|
connect_busses = X86IntelMPBusHierarchy(bus_id=0,
|
|
|
|
|
subtractive_decode=True, parent_bus=1)
|
2011-05-23 23:29:23 +02:00
|
|
|
ext_entries.append(connect_busses)
|
2009-02-01 09:26:10 +01:00
|
|
|
pci_dev4_inta = X86IntelMPIOIntAssignment(
|
|
|
|
|
interrupt_type = 'INT',
|
|
|
|
|
polarity = 'ConformPolarity',
|
|
|
|
|
trigger = 'ConformTrigger',
|
|
|
|
|
source_bus_id = 1,
|
|
|
|
|
source_bus_irq = 0 + (4 << 2),
|
2009-04-19 11:39:19 +02:00
|
|
|
dest_io_apic_id = io_apic.id,
|
2009-02-01 09:26:10 +01:00
|
|
|
dest_io_apic_intin = 16)
|
2011-05-23 23:29:23 +02:00
|
|
|
base_entries.append(pci_dev4_inta)
|
2009-04-26 11:04:32 +02:00
|
|
|
def assignISAInt(irq, apicPin):
|
|
|
|
|
assign_8259_to_apic = X86IntelMPIOIntAssignment(
|
|
|
|
|
interrupt_type = 'ExtInt',
|
|
|
|
|
polarity = 'ConformPolarity',
|
|
|
|
|
trigger = 'ConformTrigger',
|
|
|
|
|
source_bus_id = 0,
|
|
|
|
|
source_bus_irq = irq,
|
|
|
|
|
dest_io_apic_id = io_apic.id,
|
|
|
|
|
dest_io_apic_intin = 0)
|
2011-05-23 23:29:23 +02:00
|
|
|
base_entries.append(assign_8259_to_apic)
|
2009-04-26 11:04:32 +02:00
|
|
|
assign_to_apic = X86IntelMPIOIntAssignment(
|
|
|
|
|
interrupt_type = 'INT',
|
|
|
|
|
polarity = 'ConformPolarity',
|
|
|
|
|
trigger = 'ConformTrigger',
|
|
|
|
|
source_bus_id = 0,
|
|
|
|
|
source_bus_irq = irq,
|
|
|
|
|
dest_io_apic_id = io_apic.id,
|
|
|
|
|
dest_io_apic_intin = apicPin)
|
2011-05-23 23:29:23 +02:00
|
|
|
base_entries.append(assign_to_apic)
|
2009-04-26 11:04:32 +02:00
|
|
|
assignISAInt(0, 2)
|
|
|
|
|
assignISAInt(1, 1)
|
|
|
|
|
for i in range(3, 15):
|
|
|
|
|
assignISAInt(i, i)
|
2011-05-23 23:29:23 +02:00
|
|
|
self.intel_mp_table.base_entries = base_entries
|
|
|
|
|
self.intel_mp_table.ext_entries = ext_entries
|
2008-10-12 00:14:37 +02:00
|
|
|
|
2013-08-19 09:52:27 +02:00
|
|
|
def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
|
2013-04-22 19:20:33 +02:00
|
|
|
Ruby = False):
|
2008-10-10 12:50:30 +02:00
|
|
|
self = LinuxX86System()
|
|
|
|
|
|
2011-02-07 07:14:18 +01:00
|
|
|
# Build up the x86 system and then specialize it for Linux
|
2013-08-19 09:52:27 +02:00
|
|
|
makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
|
2008-10-10 12:50:30 +02:00
|
|
|
|
2008-06-12 06:58:36 +02:00
|
|
|
# We assume below that there's at least 1MB of memory. We'll require 2
|
|
|
|
|
# just to avoid corner cases.
|
2013-08-19 09:52:27 +02:00
|
|
|
phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
|
2012-09-19 12:15:41 +02:00
|
|
|
assert(phys_mem_size >= 0x200000)
|
2008-06-12 06:58:36 +02:00
|
|
|
|
2011-05-23 23:29:23 +02:00
|
|
|
self.e820_table.entries = \
|
|
|
|
|
[
|
|
|
|
|
# Mark the first megabyte of memory as reserved
|
2013-03-28 15:34:15 +01:00
|
|
|
X86E820Entry(addr = 0, size = '639kB', range_type = 1),
|
|
|
|
|
X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
|
2011-05-23 23:29:23 +02:00
|
|
|
# Mark the rest as available
|
|
|
|
|
X86E820Entry(addr = 0x100000,
|
2012-09-19 12:15:41 +02:00
|
|
|
size = '%dB' % (phys_mem_size - 0x100000),
|
2011-05-23 23:29:23 +02:00
|
|
|
range_type = 1)
|
|
|
|
|
]
|
2008-06-12 06:58:36 +02:00
|
|
|
|
2008-01-21 10:32:34 +01:00
|
|
|
# Command line
|
2009-02-01 09:29:07 +01:00
|
|
|
self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
|
2009-02-01 09:27:49 +01:00
|
|
|
'root=/dev/hda1'
|
2007-10-08 02:52:36 +02:00
|
|
|
return self
|
|
|
|
|
|
2006-11-10 00:22:46 +01:00
|
|
|
|
2012-01-28 16:24:34 +01:00
|
|
|
def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
|
|
|
|
|
self = Root(full_system = full_system)
|
2006-08-16 01:12:19 +02:00
|
|
|
self.testsys = testSystem
|
|
|
|
|
self.drivesys = driveSystem
|
2007-08-16 22:49:02 +02:00
|
|
|
self.etherlink = EtherLink()
|
|
|
|
|
self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
|
|
|
|
|
self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
|
|
|
|
|
|
2012-01-10 01:08:20 +01:00
|
|
|
if hasattr(testSystem, 'realview'):
|
|
|
|
|
self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
|
|
|
|
|
self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
|
|
|
|
|
elif hasattr(testSystem, 'tsunami'):
|
|
|
|
|
self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
|
|
|
|
|
self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
|
|
|
|
|
else:
|
|
|
|
|
fatal("Don't know how to connect these system together")
|
|
|
|
|
|
2006-08-17 04:17:23 +02:00
|
|
|
if dumpfile:
|
|
|
|
|
self.etherdump = EtherDump(file=dumpfile)
|
|
|
|
|
self.etherlink.dump = Parent.etherdump
|
|
|
|
|
|
2006-07-21 21:56:35 +02:00
|
|
|
return self
|
