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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt

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Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
---------- Begin Simulation Statistics ----------
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
sim_seconds 2.524310 # Number of seconds simulated
sim_ticks 2524309551500 # Number of ticks simulated
final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
host_inst_rate 67450 # Simulator instruction rate (inst/s)
host_op_rate 86789 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2823365435 # Simulator tick rate (ticks/s)
host_mem_usage 397608 # Number of bytes of host memory used
host_seconds 894.08 # Real time elapsed on the host
sim_insts 60305560 # Number of instructions simulated
sim_ops 77596391 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory
system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 966197440 # Total number of bytes read from memory
system.physmem.bytesWritten 52040704 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 2524308440000 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.readPktSize::6 154591 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.writePktSize::6 59118 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation
system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests
system.physmem.totBusLat 75453215000 # Total cycles spent in databus access
system.physmem.totBankLat 15307050000 # Total cycles spent in bank access
system.physmem.avgQLat 19314.15 # Average queueing delay per request
system.physmem.avgBankLat 1014.34 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.avgMemAccLat 25328.49 # Average memory access latency
system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.busUtil 3.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
system.physmem.avgWrQLen 14.41 # Average write queue length over time
system.physmem.readRowHits 15065383 # Number of row buffer hits during reads
system.physmem.writeRowHits 94229 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes
system.physmem.avgGap 158662.04 # Average gap between requests
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.throughput 54917647 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16149440 # Transaction distribution
system.membus.trans_dist::ReadResp 16149440 # Transaction distribution
system.membus.trans_dist::WriteReq 763332 # Transaction distribution
system.membus.trans_dist::WriteResp 763332 # Transaction distribution
system.membus.trans_dist::Writeback 59118 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution
system.membus.trans_dist::ReadExReq 131433 # Transaction distribution
system.membus.trans_dist::ReadExResp 131433 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 138629141 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.throughput 48301509 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution
system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution
system.iobus.trans_dist::WriteReq 8157 # Transaction distribution
system.iobus.trans_dist::WriteResp 8157 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 121927961 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.branchPred.lookups 14390442 # Number of BP lookups
system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups
system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions.
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.checker.dtb.read_hits 14986742 # DTB read hits
system.cpu.checker.dtb.read_misses 7308 # DTB read misses
system.cpu.checker.dtb.write_hits 11227334 # DTB write hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.checker.dtb.read_accesses 14994050 # DTB read accesses
system.cpu.checker.dtb.write_accesses 11229523 # DTB write accesses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.checker.dtb.hits 26214076 # DTB hits
system.cpu.checker.dtb.misses 9497 # DTB misses
system.cpu.checker.dtb.accesses 26223573 # DTB accesses
system.cpu.checker.itb.inst_hits 61479547 # ITB inst hits
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.checker.itb.inst_accesses 61484018 # ITB inst accesses
system.cpu.checker.itb.hits 61479547 # DTB hits
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.misses 4471 # DTB misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.checker.itb.accesses 61484018 # DTB accesses
system.cpu.checker.numCycles 77882185 # number of cpu cycles simulated
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dtb.read_hits 51188083 # DTB read hits
system.cpu.dtb.read_misses 64353 # DTB read misses
system.cpu.dtb.write_hits 11697459 # DTB write hits
system.cpu.dtb.write_misses 15788 # DTB write misses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 51252436 # DTB read accesses
system.cpu.dtb.write_accesses 11713247 # DTB write accesses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dtb.hits 62885542 # DTB hits
system.cpu.dtb.misses 80141 # DTB misses
system.cpu.dtb.accesses 62965683 # DTB accesses
system.cpu.itb.inst_hits 11520428 # ITB inst hits
system.cpu.itb.inst_misses 11439 # ITB inst misses
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.itb.flush_entries 4968 # Number of entries that have been flushed from TLB
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.itb.inst_accesses 11531867 # ITB inst accesses
system.cpu.itb.hits 11520428 # DTB hits
system.cpu.itb.misses 11439 # DTB misses
system.cpu.itb.accesses 11531867 # DTB accesses
system.cpu.numCycles 473080437 # number of cpu cycles simulated
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total)
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total)
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued
system.cpu.iq.rate 0.259812 # Inst issue rate
system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iew.exec_nop 221034 # number of nop insts executed
system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed
system.cpu.iew.exec_branches 11474602 # Number of branches executed
system.cpu.iew.exec_stores 12209197 # Number of stores executed
system.cpu.iew.exec_rate 0.255417 # Inst execution rate
system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back
system.cpu.iew.wb_producers 47030253 # num instructions producing a value
system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle
system.cpu.commit.committedInsts 60455941 # Number of instructions committed
system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.commit.refs 27385481 # Number of memory references committed
system.cpu.commit.loads 15653838 # Number of loads committed
system.cpu.commit.membars 403568 # Number of memory barriers committed
system.cpu.commit.branches 9961054 # Number of branches committed
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.commit.int_insts 68852229 # Number of committed integer instructions.
system.cpu.commit.function_calls 991205 # Number of function calls committed.
system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.rob.rob_reads 239241509 # The number of ROB reads
system.cpu.rob.rob_writes 195965670 # The number of ROB writes
system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 60305560 # Number of Instructions Simulated
system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated
system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads
system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 547265504 # number of integer regfile reads
system.cpu.int_regfile_writes 87536110 # number of integer regfile writes
system.cpu.fp_regfile_reads 8349 # number of floating regfile reads
system.cpu.fp_regfile_writes 2916 # number of floating regfile writes
system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads
system.cpu.misc_regfile_writes 831835 # number of misc regfile writes
system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 979660 # number of replacements
system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits
system.cpu.icache.overall_hits::total 10456897 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses
system.cpu.icache.overall_misses::total 1059959 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 64363 # number of replacements
system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits
system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses
system.cpu.l2cache.overall_misses::total 156307 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9919140742 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 644126 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1686096 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks
system.cpu.l2cache.writebacks::total 59118 # number of writebacks
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.replacements 643614 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits
system.cpu.dcache.overall_hits::total 21018772 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses
system.cpu.dcache.overall_misses::total 3700946 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks
system.cpu.dcache.writebacks::total 607864 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed
Checker: Bump the realview-o3-checker regression This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-28 20:30:25 +02:00
---------- End Simulation Statistics ----------
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