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gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt

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test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
---------- Begin Simulation Statistics ----------
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 11812000 # Number of ticks simulated
final_tick 11812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
host_inst_rate 59914 # Simulator instruction rate (inst/s)
host_op_rate 59903 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 121974515 # Simulator tick rate (ticks/s)
host_mem_usage 216016 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
sim_insts 5800 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 5800 # Number of ops (including micro ops) simulated
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory
system.physmem.bytes_read::total 28928 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory
system.physmem.num_reads::total 452 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1907213004 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 541821876 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2449034880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1907213004 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1907213004 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1907213004 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 541821876 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2449034880 # Total bandwidth to/from this memory (bytes/s)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.numCycles 23625 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.BPredUnit.lookups 2490 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 2041 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 460 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 2061 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 629 # Number of BTB hits
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 14561 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2490 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 791 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 2421 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1432 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 932 # Number of cycles fetch has spent blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.CacheLines 1897 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 11761 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.238075 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.668941 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.rateDist::0 9340 79.42% 79.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 172 1.46% 80.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 167 1.42% 82.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 146 1.24% 83.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 197 1.68% 85.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 155 1.32% 86.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 255 2.17% 88.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 108 0.92% 89.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1221 10.38% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.fetch.rateDist::total 11761 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.105397 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.616339 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 7565 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 1069 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2256 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 64 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 807 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 361 # Number of times decode resolved a branch
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.decode.DecodedInsts 12930 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 452 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 807 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 7781 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 440 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2100 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 249 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 12283 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 203 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 10602 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 20025 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 19970 # Number of integer rename lookups
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.rename.UndoneMaps 5595 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 26 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2098 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1917 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 63 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 31 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 11001 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 9282 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 167 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4968 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 4343 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 11761 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.789219 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.523023 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.issued_per_cycle::0 8303 70.60% 70.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1127 9.58% 80.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 767 6.52% 86.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 536 4.56% 91.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 478 4.06% 95.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 324 2.75% 98.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 139 1.18% 99.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 49 0.42% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 38 0.32% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.issued_per_cycle::total 11761 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.fu_full::IntAlu 5 2.87% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 78 44.83% 47.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 91 52.30% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.FU_type_0::IntAlu 5709 61.51% 61.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1861 20.05% 81.58% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1710 18.42% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.FU_type_0::total 9282 # Type of FU issued
system.cpu.iq.rate 0.392889 # Inst issue rate
system.cpu.iq.fu_busy_cnt 174 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.018746 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30604 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 16005 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8374 # Number of integer instruction queue wakeup accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iq.int_alu_accesses 9422 # Number of integer alu accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1136 # Number of loads squashed
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.lsq.thread0.squashedStores 871 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.iewSquashCycles 807 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 227 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 11066 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2098 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1917 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8779 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.exec_refs 3289 # number of memory reference insts executed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iew.exec_branches 1382 # Number of branches executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.exec_stores 1573 # Number of stores executed
system.cpu.iew.exec_rate 0.371598 # Inst execution rate
system.cpu.iew.wb_sent 8575 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8401 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4358 # num instructions producing a value
system.cpu.iew.wb_consumers 6997 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.iew.wb_rate 0.355598 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.622838 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.commitSquashedInsts 5275 # The number of squashed insts skipped by commit
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.branchMispredicts 301 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.529487 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.308345 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.committed_per_cycle::0 8509 77.68% 77.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1052 9.60% 87.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 645 5.89% 93.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 263 2.40% 95.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 183 1.67% 97.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 104 0.95% 98.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 63 0.58% 98.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 41 0.37% 99.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.committedInsts 5800 # Number of instructions committed
system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2008 # Number of memory references committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.loads 962 # Number of loads committed
system.cpu.commit.membars 7 # Number of memory barriers committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.branches 1038 # Number of branches committed
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5706 # Number of committed integer instructions.
system.cpu.commit.function_calls 103 # Number of function calls committed.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.rob.rob_reads 21935 # The number of ROB reads
system.cpu.rob.rob_writes 22958 # The number of ROB writes
system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11864 # Total number of cycles that the CPU has spent unscheduled due to idling
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.committedInsts 5800 # Number of Instructions Simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.committedInsts_total 5800 # Number of Instructions Simulated
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.cpi 4.073276 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.073276 # CPI: Total CPI of All Threads
system.cpu.ipc 0.245503 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.245503 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 13900 # number of integer regfile reads
system.cpu.int_regfile_writes 7266 # number of integer regfile writes
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.replacements 0 # number of replacements
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.tagsinuse 172.776641 # Cycle average of tags in use
system.cpu.icache.total_refs 1462 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 357 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.095238 # Average number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.occ_blocks::cpu.inst 172.776641 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.084364 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.084364 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits
system.cpu.icache.overall_hits::total 1462 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses
system.cpu.icache.overall_misses::total 435 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16386000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16386000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16386000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16386000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16386000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16386000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1897 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1897 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1897 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1897 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1897 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1897 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229309 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.229309 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.229309 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.229309 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.229309 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.229309 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37668.965517 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 37668.965517 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37668.965517 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 37668.965517 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37668.965517 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 37668.965517 # average overall miss latency
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 78 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 78 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 78 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 357 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 357 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 357 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 357 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 357 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13154500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 13154500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13154500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 13154500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13154500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 13154500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188192 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.188192 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.188192 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36847.338936 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36847.338936 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36847.338936 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36847.338936 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36847.338936 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36847.338936 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.tagsinuse 63.298936 # Cycle average of tags in use
system.cpu.dcache.total_refs 2197 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 100 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 21.970000 # Average number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.occ_blocks::cpu.data 63.298936 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.015454 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.015454 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1480 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1480 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 717 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 717 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2197 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2197 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2197 # number of overall hits
system.cpu.dcache.overall_hits::total 2197 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 92 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 92 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 329 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 329 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 421 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 421 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 421 # number of overall misses
system.cpu.dcache.overall_misses::total 421 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3732500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3732500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12822500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12822500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 16555000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 16555000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 16555000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 16555000 # number of overall miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.ReadReq_accesses::cpu.data 1572 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1572 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.demand_accesses::cpu.data 2618 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2618 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2618 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2618 # number of overall (read+write) accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058524 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.058524 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314532 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.314532 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.160810 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.160810 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.160810 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.160810 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40570.652174 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40570.652174 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38974.164134 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38974.164134 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39323.040380 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39323.040380 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39323.040380 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39323.040380 # average overall miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 39 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 282 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 282 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 321 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 321 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 321 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 321 # number of overall MSHR hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 100 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 100 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 100 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 100 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2119000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2119000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2085000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2085000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4204000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 4204000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4204000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 4204000 # number of overall MSHR miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033715 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033715 # mshr miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038197 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.038197 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038197 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.038197 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39981.132075 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39981.132075 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.702128 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.702128 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42040 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 42040 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42040 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 42040 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.tagsinuse 203.410235 # Cycle average of tags in use
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.sampled_refs 405 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.012346 # Average number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.occ_blocks::cpu.inst 171.891736 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.518500 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005246 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006208 # Average percentage of cache occupancy
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
system.cpu.l2cache.overall_hits::total 5 # number of overall hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 352 # number of ReadReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_misses::total 405 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 352 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 100 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 452 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 352 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 100 # number of overall misses
system.cpu.l2cache.overall_misses::total 452 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12780500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2060500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 14841000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2028000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2028000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 12780500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4088500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 16869000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 12780500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4088500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 16869000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 357 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 357 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 100 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 357 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 100 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985994 # miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.987805 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985994 # miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.989059 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985994 # miss rate for overall accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.989059 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36308.238636 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38877.358491 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36644.444444 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43148.936170 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43148.936170 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36308.238636 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40885 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 37320.796460 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36308.238636 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40885 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 37320.796460 # average overall miss latency
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 352 # number of ReadReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 405 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 352 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 100 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 352 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 100 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11653500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1896000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13549500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1881500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1881500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11653500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3777500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15431000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11653500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3777500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15431000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987805 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.989059 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.989059 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.534091 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35773.584906 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33455.555556 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40031.914894 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40031.914894 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing.
2009-10-27 17:24:40 +01:00
---------- End Simulation Statistics ----------
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