2010-01-30 05:29:40 +01:00
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================ Begin RubySystem Configuration Print ================
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RubySystem config:
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random_seed: 1234
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randomization: 1
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cycle_period: 1
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block_size_bytes: 64
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block_size_bits: 6
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memory_size_bytes: 134217728
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memory_size_bits: 27
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Network Configuration
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---------------------
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network: SIMPLE_NETWORK
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2011-02-08 04:23:13 +01:00
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topology:
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2010-01-30 05:29:40 +01:00
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virtual_net_0: active, ordered
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virtual_net_1: active, ordered
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virtual_net_2: active, ordered
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2010-03-22 05:22:22 +01:00
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virtual_net_3: active, ordered
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2010-01-30 05:29:40 +01:00
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virtual_net_4: active, ordered
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2010-03-22 05:22:22 +01:00
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virtual_net_5: inactive
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2010-01-30 05:29:40 +01:00
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virtual_net_6: inactive
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virtual_net_7: inactive
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virtual_net_8: inactive
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virtual_net_9: inactive
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Profiler Configuration
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----------------------
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periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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2012-06-05 07:23:16 +02:00
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Real time: Jun/04/2012 13:52:42
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2010-01-30 05:29:40 +01:00
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Profiler Stats
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--------------
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2012-05-09 20:52:14 +02:00
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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2010-01-30 05:29:40 +01:00
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2012-06-05 07:23:16 +02:00
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Virtual_time_in_seconds: 0.28
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Virtual_time_in_minutes: 0.00466667
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Virtual_time_in_hours: 7.77778e-05
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Virtual_time_in_days: 3.24074e-06
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2010-01-30 05:29:40 +01:00
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2012-04-07 01:16:24 +02:00
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Ruby_current_time: 280571
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2010-01-30 05:29:40 +01:00
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Ruby_start_time: 0
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2012-04-07 01:16:24 +02:00
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Ruby_cycles: 280571
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2010-01-30 05:29:40 +01:00
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2012-06-05 07:23:16 +02:00
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mbytes_resident: 43.0117
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mbytes_total: 215.34
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resident_ratio: 0.199739
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2010-01-30 05:29:40 +01:00
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2012-04-07 01:16:24 +02:00
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ruby_cycles_executed: [ 280572 ]
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2010-01-30 05:29:40 +01:00
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Busy Controller Counts:
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L1Cache-0:0
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Directory-0:0
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Busy Bank Count:0
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2012-04-07 01:16:24 +02:00
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sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1000 average: 15.774 | standard deviation: 1.14469 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 8 93 886 ]
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2010-01-30 05:29:40 +01:00
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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2012-04-07 01:16:24 +02:00
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miss_latency: [binsize: 32 max: 6185 count: 986 average: 4512.83 | standard deviation: 564.917 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 0 2 0 1 1 1 0 3 0 1 1 2 5 4 6 5 8 7 2 12 9 11 7 16 19 21 19 24 15 26 28 20 22 22 30 33 30 27 30 31 27 29 27 19 18 31 35 23 21 29 18 15 18 17 12 17 5 13 10 2 9 7 5 6 6 5 5 6 4 1 2 3 1 1 0 3 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
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miss_latency_LD: [binsize: 32 max: 5593 count: 43 average: 4526 | standard deviation: 440.983 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 2 2 2 1 1 1 1 1 0 1 1 0 3 1 0 1 1 2 2 1 0 2 1 1 1 2 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 1 ]
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miss_latency_ST: [binsize: 32 max: 6185 count: 886 average: 4517.13 | standard deviation: 578.837 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 0 2 0 1 1 1 0 2 0 1 1 2 5 4 6 4 6 4 2 12 9 10 5 15 13 17 16 20 14 20 25 18 21 19 29 32 26 25 26 30 26 26 25 16 17 28 32 21 17 25 17 14 15 16 11 17 5 9 8 2 9 7 5 6 5 5 5 4 4 1 2 3 0 1 0 3 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
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miss_latency_IFETCH: [binsize: 32 max: 5314 count: 57 average: 4436.05 | standard deviation: 407.417 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 3 0 0 0 0 1 1 4 2 1 3 0 5 2 1 1 2 0 1 1 1 4 0 0 1 0 2 1 1 2 1 3 2 1 0 2 1 0 0 0 3 1 0 0 0 0 0 1 ]
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miss_latency_L1Cache: [binsize: 32 max: 5682 count: 39 average: 3989.69 | standard deviation: 543.603 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0 2 0 0 1 0 2 1 1 2 1 1 0 3 1 0 0 0 0 1 2 0 0 0 2 1 2 0 1 0 0 2 0 1 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_Directory: [binsize: 32 max: 6185 count: 947 average: 4534.38 | standard deviation: 555.581 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 3 3 5 3 7 6 2 9 8 11 7 16 19 20 17 24 15 26 26 19 20 22 29 33 30 25 30 30 27 29 27 18 18 29 35 23 21 29 18 15 18 17 11 17 5 13 10 2 9 7 5 6 6 5 5 6 4 1 2 3 1 1 0 2 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
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2010-08-21 02:44:26 +02:00
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_wCC_Times: 0
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miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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2012-04-07 01:16:24 +02:00
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imcomplete_dir_Times: 947
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miss_latency_LD_Directory: [binsize: 32 max: 5593 count: 43 average: 4526 | standard deviation: 440.983 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 2 2 2 1 1 1 1 1 0 1 1 0 3 1 0 1 1 2 2 1 0 2 1 1 1 2 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 1 ]
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miss_latency_ST_L1Cache: [binsize: 32 max: 5682 count: 37 average: 4008.19 | standard deviation: 551.275 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 1 0 2 1 1 2 0 1 0 3 1 0 0 0 0 1 2 0 0 0 2 1 2 0 1 0 0 2 0 1 0 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_ST_Directory: [binsize: 32 max: 6185 count: 849 average: 4539.31 | standard deviation: 570.066 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 2 3 3 5 2 6 3 2 9 8 10 5 15 13 16 14 20 14 20 23 17 19 19 28 32 26 23 26 29 26 26 25 15 17 26 32 21 17 25 17 14 15 16 10 17 5 9 8 2 9 7 5 6 5 5 5 4 4 1 2 3 0 1 0 2 1 4 3 0 1 0 1 4 2 0 0 1 1 0 0 1 ]
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miss_latency_IFETCH_L1Cache: [binsize: 32 max: 3792 count: 2 average: 3647.5 | standard deviation: 204.355 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
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miss_latency_IFETCH_Directory: [binsize: 32 max: 5314 count: 55 average: 4464.73 | standard deviation: 384.051 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 1 4 2 1 3 0 5 2 1 1 2 0 1 1 1 4 0 0 1 0 2 1 1 2 1 3 2 1 0 2 1 0 0 0 3 1 0 0 0 0 0 1 ]
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2010-01-30 05:29:40 +01:00
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
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2012-04-07 01:16:24 +02:00
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Total_delay_cycles: [binsize: 1 max: 8 count: 1890 average: 0.140212 | standard deviation: 0.700147 | 1792 21 32 25 7 8 1 1 3 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 8 count: 1890 average: 0.140212 | standard deviation: 0.700147 | 1792 21 32 25 7 8 1 1 3 ]
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2010-01-30 05:29:40 +01:00
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virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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2012-04-07 01:16:24 +02:00
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virtual_network_1_delay_cycles: [binsize: 1 max: 8 count: 947 average: 0.198522 | standard deviation: 0.78638 | 871 19 27 18 5 5 0 0 2 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 8 count: 943 average: 0.0816543 | standard deviation: 0.596344 | 921 2 5 7 2 3 1 1 1 ]
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2010-01-30 05:29:40 +01:00
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Resource Usage
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--------------
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page_size: 4096
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user_time: 0
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system_time: 0
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2012-06-05 07:23:16 +02:00
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page_reclaims: 11376
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page_faults: 5
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2010-01-30 05:29:40 +01:00
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swaps: 0
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2012-06-05 07:23:16 +02:00
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block_inputs: 432
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block_outputs: 80
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2010-01-30 05:29:40 +01:00
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Network Stats
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-------------
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2012-04-07 01:16:24 +02:00
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total_msg_count_Control: 2841 22728
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total_msg_count_Data: 2833 203976
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total_msg_count_Response_Data: 2841 204552
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total_msg_count_Writeback_Control: 2829 22632
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total_msgs: 11344 total_bytes: 453888
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2010-08-21 02:44:26 +02:00
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2010-01-30 05:29:40 +01:00
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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2012-04-07 01:16:24 +02:00
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links_utilized_percent_switch_0: 1.68505
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links_utilized_percent_switch_0_link_0: 1.68692 bw: 16000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 1.68317 bw: 16000 base_latency: 1
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2010-01-30 05:29:40 +01:00
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2012-04-07 01:16:24 +02:00
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outgoing_messages_switch_0_link_0_Response_Data: 947 68184 [ 0 0 0 0 947 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Writeback_Control: 943 7544 [ 0 0 0 943 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Control: 947 7576 [ 0 0 947 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Data: 945 68040 [ 0 0 945 0 0 0 0 0 0 0 ] base_latency: 1
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2010-01-30 05:29:40 +01:00
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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2012-04-07 01:16:24 +02:00
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links_utilized_percent_switch_1: 1.68487
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links_utilized_percent_switch_1_link_0: 1.68282 bw: 16000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 1.68692 bw: 16000 base_latency: 1
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2010-01-30 05:29:40 +01:00
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2012-04-07 01:16:24 +02:00
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outgoing_messages_switch_1_link_0_Control: 947 7576 [ 0 0 947 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Data: 944 67968 [ 0 0 944 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 947 68184 [ 0 0 0 0 947 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Control: 943 7544 [ 0 0 0 943 0 0 0 0 0 0 ] base_latency: 1
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2010-01-30 05:29:40 +01:00
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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2012-04-07 01:16:24 +02:00
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links_utilized_percent_switch_2: 1.68487
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links_utilized_percent_switch_2_link_0: 1.68692 bw: 16000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 1.68282 bw: 16000 base_latency: 1
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2010-01-30 05:29:40 +01:00
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2012-04-07 01:16:24 +02:00
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outgoing_messages_switch_2_link_0_Response_Data: 947 68184 [ 0 0 0 0 947 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Writeback_Control: 943 7544 [ 0 0 0 943 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Control: 947 7576 [ 0 0 947 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Data: 944 67968 [ 0 0 944 0 0 0 0 0 0 0 ] base_latency: 1
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2010-01-30 05:29:40 +01:00
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2012-01-25 18:19:50 +01:00
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Cache Stats: system.l1_cntrl0.cacheMemory
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2012-04-07 01:16:24 +02:00
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system.l1_cntrl0.cacheMemory_total_misses: 949
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system.l1_cntrl0.cacheMemory_total_demand_misses: 949
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2012-01-25 18:19:50 +01:00
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system.l1_cntrl0.cacheMemory_total_prefetches: 0
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system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
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system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
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2010-01-30 05:29:40 +01:00
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2012-04-07 01:16:24 +02:00
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system.l1_cntrl0.cacheMemory_request_type_LD: 4.63646%
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system.l1_cntrl0.cacheMemory_request_type_ST: 89.568%
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system.l1_cntrl0.cacheMemory_request_type_IFETCH: 5.79557%
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2010-01-30 05:29:40 +01:00
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2012-04-07 01:16:24 +02:00
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system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 949 100%
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2010-01-30 05:29:40 +01:00
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2010-08-21 02:44:26 +02:00
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--- L1Cache ---
|
2010-01-30 05:29:40 +01:00
|
|
|
- Event Counts -
|
2012-04-07 01:16:24 +02:00
|
|
|
Load [44 ] 44
|
|
|
|
Ifetch [57 ] 57
|
|
|
|
Store [887 ] 887
|
|
|
|
Data [947 ] 947
|
2010-08-21 02:44:26 +02:00
|
|
|
Fwd_GETX [0 ] 0
|
|
|
|
Inv [0 ] 0
|
2012-04-07 01:16:24 +02:00
|
|
|
Replacement [946 ] 946
|
|
|
|
Writeback_Ack [943 ] 943
|
2010-08-21 02:44:26 +02:00
|
|
|
Writeback_Nack [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
|
|
|
- Transitions -
|
2012-04-07 01:16:24 +02:00
|
|
|
I Load [44 ] 44
|
|
|
|
I Ifetch [55 ] 55
|
|
|
|
I Store [850 ] 850
|
2010-08-21 02:44:26 +02:00
|
|
|
I Inv [0 ] 0
|
|
|
|
I Replacement [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2010-08-21 02:44:26 +02:00
|
|
|
II Writeback_Nack [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2012-04-07 01:16:24 +02:00
|
|
|
M Load [0 ] 0
|
|
|
|
M Ifetch [2 ] 2
|
|
|
|
M Store [37 ] 37
|
2010-08-21 02:44:26 +02:00
|
|
|
M Fwd_GETX [0 ] 0
|
|
|
|
M Inv [0 ] 0
|
2012-04-07 01:16:24 +02:00
|
|
|
M Replacement [946 ] 946
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2010-08-21 02:44:26 +02:00
|
|
|
MI Fwd_GETX [0 ] 0
|
|
|
|
MI Inv [0 ] 0
|
2012-04-07 01:16:24 +02:00
|
|
|
MI Writeback_Ack [943 ] 943
|
2010-08-21 02:44:26 +02:00
|
|
|
MI Writeback_Nack [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2010-08-21 02:44:26 +02:00
|
|
|
MII Fwd_GETX [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2010-08-21 02:44:26 +02:00
|
|
|
IS Data [98 ] 98
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2012-04-07 01:16:24 +02:00
|
|
|
IM Data [849 ] 849
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2010-08-21 02:44:26 +02:00
|
|
|
Memory controller: system.dir_cntrl0.memBuffer:
|
2012-04-07 01:16:24 +02:00
|
|
|
memory_total_requests: 1891
|
|
|
|
memory_reads: 947
|
|
|
|
memory_writes: 944
|
|
|
|
memory_refreshes: 585
|
|
|
|
memory_total_request_delays: 2814
|
|
|
|
memory_delays_per_request: 1.4881
|
|
|
|
memory_delays_in_input_queue: 676
|
|
|
|
memory_delays_behind_head_of_bank_queue: 12
|
|
|
|
memory_delays_stalled_at_head_of_bank_queue: 2126
|
|
|
|
memory_stalls_for_bank_busy: 294
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_random_busy: 0
|
|
|
|
memory_stalls_for_anti_starvation: 0
|
2012-04-07 01:16:24 +02:00
|
|
|
memory_stalls_for_arbitration: 265
|
|
|
|
memory_stalls_for_bus: 935
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_tfaw: 0
|
2012-04-07 01:16:24 +02:00
|
|
|
memory_stalls_for_read_write_turnaround: 518
|
|
|
|
memory_stalls_for_read_read_turnaround: 114
|
|
|
|
accesses_per_bank: 46 50 40 88 149 74 58 50 50 48 58 62 54 60 56 58 60 62 54 54 63 54 56 44 54 77 52 48 46 62 46 58
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2010-08-21 02:44:26 +02:00
|
|
|
--- Directory ---
|
2010-01-30 05:29:40 +01:00
|
|
|
- Event Counts -
|
2012-04-07 01:16:24 +02:00
|
|
|
GETX [947 ] 947
|
2010-08-21 02:44:26 +02:00
|
|
|
GETS [0 ] 0
|
2012-04-07 01:16:24 +02:00
|
|
|
PUTX [944 ] 944
|
2010-08-21 02:44:26 +02:00
|
|
|
PUTX_NotOwner [0 ] 0
|
|
|
|
DMA_READ [0 ] 0
|
|
|
|
DMA_WRITE [0 ] 0
|
2012-04-07 01:16:24 +02:00
|
|
|
Memory_Data [947 ] 947
|
|
|
|
Memory_Ack [944 ] 944
|
2010-01-30 05:29:40 +01:00
|
|
|
|
|
|
|
- Transitions -
|
2012-04-07 01:16:24 +02:00
|
|
|
I GETX [947 ] 947
|
2010-08-21 02:44:26 +02:00
|
|
|
I PUTX_NotOwner [0 ] 0
|
|
|
|
I DMA_READ [0 ] 0
|
|
|
|
I DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
M GETX [0 ] 0
|
2012-04-07 01:16:24 +02:00
|
|
|
M PUTX [944 ] 944
|
2010-08-21 02:44:26 +02:00
|
|
|
M PUTX_NotOwner [0 ] 0
|
|
|
|
M DMA_READ [0 ] 0
|
|
|
|
M DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
M_DRD GETX [0 ] 0
|
|
|
|
M_DRD PUTX [0 ] 0
|
|
|
|
|
|
|
|
M_DWR GETX [0 ] 0
|
|
|
|
M_DWR PUTX [0 ] 0
|
|
|
|
|
|
|
|
M_DWRI GETX [0 ] 0
|
|
|
|
M_DWRI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
M_DRDI GETX [0 ] 0
|
|
|
|
M_DRDI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
IM GETX [0 ] 0
|
|
|
|
IM GETS [0 ] 0
|
|
|
|
IM PUTX [0 ] 0
|
|
|
|
IM PUTX_NotOwner [0 ] 0
|
|
|
|
IM DMA_READ [0 ] 0
|
|
|
|
IM DMA_WRITE [0 ] 0
|
2012-04-07 01:16:24 +02:00
|
|
|
IM Memory_Data [947 ] 947
|
2010-08-21 02:44:26 +02:00
|
|
|
|
|
|
|
MI GETX [0 ] 0
|
|
|
|
MI GETS [0 ] 0
|
|
|
|
MI PUTX [0 ] 0
|
|
|
|
MI PUTX_NotOwner [0 ] 0
|
|
|
|
MI DMA_READ [0 ] 0
|
|
|
|
MI DMA_WRITE [0 ] 0
|
2012-04-07 01:16:24 +02:00
|
|
|
MI Memory_Ack [944 ] 944
|
2010-08-21 02:44:26 +02:00
|
|
|
|
|
|
|
ID GETX [0 ] 0
|
|
|
|
ID GETS [0 ] 0
|
|
|
|
ID PUTX [0 ] 0
|
|
|
|
ID PUTX_NotOwner [0 ] 0
|
|
|
|
ID DMA_READ [0 ] 0
|
|
|
|
ID DMA_WRITE [0 ] 0
|
|
|
|
ID Memory_Data [0 ] 0
|
|
|
|
|
|
|
|
ID_W GETX [0 ] 0
|
|
|
|
ID_W GETS [0 ] 0
|
|
|
|
ID_W PUTX [0 ] 0
|
|
|
|
ID_W PUTX_NotOwner [0 ] 0
|
|
|
|
ID_W DMA_READ [0 ] 0
|
|
|
|
ID_W DMA_WRITE [0 ] 0
|
2012-01-25 18:19:50 +01:00
|
|
|
ID_W Memory_Ack [0 ] 0
|
|
|
|
|