2011-06-21 04:44:24 +02:00
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---------- Begin Simulation Statistics ----------
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2013-05-30 18:54:18 +02:00
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sim_seconds 0.000027 # Number of seconds simulated
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sim_ticks 27167500 # Number of ticks simulated
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final_tick 27167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-06-21 04:44:24 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2013-05-30 18:54:18 +02:00
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host_inst_rate 49297 # Simulator instruction rate (inst/s)
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host_op_rate 49293 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 88314525 # Simulator tick rate (ticks/s)
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host_mem_usage 232472 # Number of bytes of host memory used
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host_seconds 0.31 # Real time elapsed on the host
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2012-08-15 16:38:05 +02:00
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sim_insts 15162 # Number of instructions simulated
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sim_ops 15162 # Number of ops (including micro ops) simulated
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2012-06-05 07:23:16 +02:00
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system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27904 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 19072 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 19072 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
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2013-05-30 18:54:18 +02:00
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system.physmem.bw_read::cpu.inst 702015276 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 325094322 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1027109598 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 702015276 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 702015276 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 702015276 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 325094322 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1027109598 # Total bandwidth to/from this memory (bytes/s)
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2012-10-25 19:14:42 +02:00
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system.physmem.readReqs 436 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 27904 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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2013-05-30 18:54:18 +02:00
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system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 38 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 20 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 29 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 58 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 33 # Track reads on a per bank basis
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2012-10-25 19:14:42 +02:00
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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2013-05-30 18:54:18 +02:00
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system.physmem.totGap 27134000 # Total gap between requests
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2012-10-25 19:14:42 +02:00
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 436 # Categorize read packet sizes
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2013-03-01 19:20:30 +01:00
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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2013-05-30 18:54:18 +02:00
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system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 116 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
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2012-10-30 14:35:32 +01:00
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system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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2013-05-30 18:54:18 +02:00
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system.physmem.bytesPerActivate::samples 49 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 344.816327 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 179.016062 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 498.456939 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 18 36.73% 36.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 9 18.37% 55.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 3 6.12% 61.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 5 10.20% 71.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 3 6.12% 77.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384 1 2.04% 79.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448 1 2.04% 81.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576 2 4.08% 85.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704 1 2.04% 87.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768 1 2.04% 89.80% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896 1 2.04% 91.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600 1 2.04% 93.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation
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system.physmem.totQLat 1645750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 10137000 # Sum of mem lat for all requests
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2013-01-31 13:49:16 +01:00
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system.physmem.totBusLat 2180000 # Total cycles spent in databus access
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2013-05-30 18:54:18 +02:00
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system.physmem.totBankLat 6311250 # Total cycles spent in bank access
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system.physmem.avgQLat 3774.66 # Average queueing delay per request
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system.physmem.avgBankLat 14475.34 # Average bank access latency per request
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2013-01-31 13:49:16 +01:00
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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2013-05-30 18:54:18 +02:00
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system.physmem.avgMemAccLat 23250.00 # Average memory access latency
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system.physmem.avgRdBW 1027.11 # Average achieved read bandwidth in MB/s
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2012-10-25 19:14:42 +02:00
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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2013-05-30 18:54:18 +02:00
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system.physmem.avgConsumedRdBW 1027.11 # Average consumed read bandwidth in MB/s
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2012-10-25 19:14:42 +02:00
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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2013-01-31 13:49:16 +01:00
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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2013-05-30 18:54:18 +02:00
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system.physmem.busUtil 8.02 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.37 # Average read queue length over time
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2012-10-25 19:14:42 +02:00
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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2013-05-30 18:54:18 +02:00
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system.physmem.readRowHits 387 # Number of row buffer hits during reads
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2012-10-25 19:14:42 +02:00
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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2013-05-30 18:54:18 +02:00
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system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads
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2012-10-25 19:14:42 +02:00
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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2013-05-30 18:54:18 +02:00
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system.physmem.avgGap 62233.94 # Average gap between requests
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system.membus.throughput 1024753842 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 351 # Transaction distribution
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system.membus.trans_dist::ReadResp 350 # Transaction distribution
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system.membus.trans_dist::ReadExReq 85 # Transaction distribution
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system.membus.trans_dist::ReadExResp 85 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 871 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 871 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27840 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 27840 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 27840 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
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system.membus.respLayer1.occupancy 4057250 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 14.9 # Layer utilization (%)
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2013-01-31 13:49:16 +01:00
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system.cpu.branchPred.lookups 5146 # Number of BP lookups
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2013-01-24 19:29:00 +01:00
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system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect
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2013-01-31 13:49:16 +01:00
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system.cpu.branchPred.BTBLookups 4100 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 2719 # Number of BTB hits
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2013-01-24 19:29:00 +01:00
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.branchPred.BTBHitPct 66.317073 # BTB Hit Percentage
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
|
|
|
|
system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.workload.num_syscalls 18 # Number of system calls
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.numCycles 54336 # number of cpu cycles simulated
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True).
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False).
|
|
|
|
system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.regfile_manager.intRegFileAccesses 25496 # Total Accesses (Read+Write) to the Int. Register File
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
|
|
|
|
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
|
|
|
|
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.regfile_manager.regForwards 5052 # Number of Registers Read Through Forwarding Logic
|
|
|
|
system.cpu.agen_unit.agens 3844 # Number of Address Generations
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.execution_unit.predictedTakenIncorrect 1541 # Number of Branches Incorrectly Predicted As Taken.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 762 # Number of Branches Incorrectly Predicted As Not Taken).
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.execution_unit.mispredicted 2303 # Number of Branches Incorrectly Predicted
|
|
|
|
system.cpu.execution_unit.predicted 1055 # Number of Branches Incorrectly Predicted
|
|
|
|
system.cpu.execution_unit.mispredictPct 68.582490 # Percentage of Incorrect Branches Predicts
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.execution_unit.executions 11045 # Number of Instructions Executed.
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
|
|
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.threadCycles 21896 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
system.cpu.idleCycles 36768 # Number of cycles cpu's stages were not processed
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.runCycles 17568 # Number of cycles cpu stages are processed.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.activity 32.332155 # Percentage of cycles cpu is active
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.comLoads 2225 # Number of Load instructions committed
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.comStores 1448 # Number of Store instructions committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.comBranches 3358 # Number of Branches instructions committed
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.comNops 726 # Number of Nop instructions committed
|
|
|
|
system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.comInts 7166 # Number of Integer instructions committed
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.comFloats 0 # Number of Floating Point instructions committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.committedInsts 15162 # Number of Instructions committed (Per-Thread)
|
|
|
|
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.cpi 3.583696 # CPI: Cycles Per Instruction (Per-Thread)
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.cpi_total 3.583696 # CPI: Total CPI of All Threads
|
|
|
|
system.cpu.ipc 0.279042 # IPC: Instructions Per Cycle (Per-Thread)
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.ipc_total 0.279042 # IPC: Total IPC of All Threads
|
|
|
|
system.cpu.stage0.idleCycles 40910 # Number of cycles 0 instructions are processed.
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.stage0.utilization 24.709217 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
system.cpu.stage1.idleCycles 44983 # Number of cycles 0 instructions are processed.
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.stage1.utilization 17.213266 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
system.cpu.stage2.idleCycles 45533 # Number of cycles 0 instructions are processed.
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.stage2.utilization 16.201045 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
system.cpu.stage3.idleCycles 51458 # Number of cycles 0 instructions are processed.
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.stage3.utilization 5.296673 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
system.cpu.stage4.idleCycles 45027 # Number of cycles 0 instructions are processed.
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.stage4.utilization 17.132288 # Percentage of cycles stage was utilized (processing insts).
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.icache.tagsinuse 168.384950 # Cycle average of tags in use
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.icache.total_refs 3004 # Total number of references to valid blocks.
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks.
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 168.384950 # Average occupied blocks per requestor
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.082219 # Average percentage of cache occupancy
|
|
|
|
system.cpu.icache.occ_percent::total 0.082219 # Average percentage of cache occupancy
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits
|
|
|
|
system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits
|
|
|
|
system.cpu.icache.demand_hits::total 3004 # number of demand (read+write) hits
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 3004 # number of overall hits
|
|
|
|
system.cpu.icache.overall_hits::total 3004 # number of overall hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 381 # number of ReadReq misses
|
|
|
|
system.cpu.icache.ReadReq_misses::total 381 # number of ReadReq misses
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 381 # number of demand (read+write) misses
|
|
|
|
system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
|
|
|
|
system.cpu.icache.overall_misses::total 381 # number of overall misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25319500 # number of ReadReq miss cycles
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 25319500 # number of ReadReq miss cycles
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 25319500 # number of demand (read+write) miss cycles
|
|
|
|
system.cpu.icache.demand_miss_latency::total 25319500 # number of demand (read+write) miss cycles
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 25319500 # number of overall miss cycles
|
|
|
|
system.cpu.icache.overall_miss_latency::total 25319500 # number of overall miss cycles
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
|
|
|
|
system.cpu.icache.demand_accesses::total 3385 # number of demand (read+write) accesses
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 3385 # number of overall (read+write) accesses
|
|
|
|
system.cpu.icache.overall_accesses::total 3385 # number of overall (read+write) accesses
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112555 # miss rate for ReadReq accesses
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.112555 # miss rate for ReadReq accesses
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 # miss rate for demand accesses
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66455.380577 # average ReadReq miss latency
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 66455.380577 # average ReadReq miss latency
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 66455.380577 # average overall miss latency
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 66455.380577 # average overall miss latency
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20038500 # number of ReadReq MSHR miss cycles
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 20038500 # number of ReadReq MSHR miss cycles
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20038500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 20038500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20038500 # number of overall MSHR miss cycles
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 20038500 # number of overall MSHR miss cycles
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66573.089701 # average ReadReq mshr miss latency
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66573.089701 # average ReadReq mshr miss latency
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.throughput 1029465354 # Throughput (bytes/s)
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 600 # Packet count per connected master and slave (bytes)
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
|
|
|
|
system.cpu.toL2Bus.pkt_count 876 # Packet count per connected master and slave (bytes)
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19136 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
|
|
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
|
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 448500 # Layer occupancy (ticks)
|
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
|
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
|
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 199.348050 # Cycle average of tags in use
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks.
|
|
|
|
system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks.
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 167.722707 # Average occupied blocks per requestor
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 31.625344 # Average occupied blocks per requestor
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.006084 # Average percentage of cache occupancy
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 299 # number of ReadReq misses
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 352 # number of ReadReq misses
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 299 # number of demand (read+write) misses
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
|
|
|
|
system.cpu.l2cache.demand_misses::total 437 # number of demand (read+write) misses
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
|
|
|
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19715000 # number of ReadReq miss cycles
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3728500 # number of ReadReq miss cycles
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 23443500 # number of ReadReq miss cycles
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5878000 # number of ReadExReq miss cycles
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5878000 # number of ReadExReq miss cycles
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 19715000 # number of demand (read+write) miss cycles
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9606500 # number of demand (read+write) miss cycles
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 29321500 # number of demand (read+write) miss cycles
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 19715000 # number of overall miss cycles
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9606500 # number of overall miss cycles
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 29321500 # number of overall miss cycles
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 301 # number of demand (read+write) accesses
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
|
|
|
|
system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 301 # number of overall (read+write) accesses
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
|
|
|
|
system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.994350 # miss rate for ReadReq accesses
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.995444 # miss rate for demand accesses
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.454849 # average ReadReq miss latency
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70349.056604 # average ReadReq miss latency
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66600.852273 # average ReadReq miss latency
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69152.941176 # average ReadExReq miss latency
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69152.941176 # average ReadExReq miss latency
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 67097.254005 # average overall miss latency
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 67097.254005 # average overall miss latency
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16042000 # number of ReadReq MSHR miss cycles
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076500 # number of ReadReq MSHR miss cycles
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19118500 # number of ReadReq MSHR miss cycles
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16042000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7917250 # number of demand (read+write) MSHR miss cycles
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 23959250 # number of demand (read+write) MSHR miss cycles
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16042000 # number of overall MSHR miss cycles
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7917250 # number of overall MSHR miss cycles
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 23959250 # number of overall MSHR miss cycles
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53652.173913 # average ReadReq mshr miss latency
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58047.169811 # average ReadReq mshr miss latency
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54313.920455 # average ReadReq mshr miss latency
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.dcache.tagsinuse 98.129274 # Cycle average of tags in use
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks.
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks.
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 98.129274 # Average occupied blocks per requestor
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.023957 # Average percentage of cache occupancy
|
|
|
|
system.cpu.dcache.occ_percent::total 0.023957 # Average percentage of cache occupancy
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
|
|
|
|
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits
|
|
|
|
system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits
|
|
|
|
system.cpu.dcache.overall_hits::total 3187 # number of overall hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 422 # number of WriteReq misses
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 422 # number of WriteReq misses
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses
|
|
|
|
system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses
|
|
|
|
system.cpu.dcache.overall_misses::total 480 # number of overall misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4284500 # number of ReadReq miss cycles
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4284500 # number of ReadReq miss cycles
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25306500 # number of WriteReq miss cycles
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 25306500 # number of WriteReq miss cycles
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 29591000 # number of demand (read+write) miss cycles
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 29591000 # number of demand (read+write) miss cycles
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 29591000 # number of overall miss cycles
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 29591000 # number of overall miss cycles
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
|
|
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
|
|
|
|
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
|
|
|
|
system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
|
|
|
|
system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73870.689655 # average ReadReq miss latency
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 73870.689655 # average ReadReq miss latency
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.009479 # average WriteReq miss latency
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.009479 # average WriteReq miss latency
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 61647.916667 # average overall miss latency
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 61647.916667 # average overall miss latency
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 1016 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.882353 # average number of cycles each access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3783000 # number of ReadReq MSHR miss cycles
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3783000 # number of ReadReq MSHR miss cycles
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5966000 # number of WriteReq MSHR miss cycles
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5966000 # number of WriteReq MSHR miss cycles
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9749000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 9749000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9749000 # number of overall MSHR miss cycles
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 9749000 # number of overall MSHR miss cycles
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71377.358491 # average ReadReq mshr miss latency
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71377.358491 # average ReadReq mshr miss latency
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70188.235294 # average WriteReq mshr miss latency
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70188.235294 # average WriteReq mshr miss latency
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency
|
2011-06-21 04:44:24 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|