2010-07-27 07:03:44 +02:00
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2011-03-18 01:20:22 +01:00
|
|
|
sim_seconds 0.054241 # Number of seconds simulated
|
2012-06-29 17:19:03 +02:00
|
|
|
sim_ticks 54240661000 # Number of ticks simulated
|
|
|
|
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2012-01-25 18:19:50 +01:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2014-01-24 22:29:34 +01:00
|
|
|
host_inst_rate 2151308 # Simulator instruction rate (inst/s)
|
|
|
|
host_op_rate 2166754 # Simulator op (including micro ops) rate (op/s)
|
|
|
|
host_tick_rate 1287915883 # Simulator tick rate (ticks/s)
|
|
|
|
host_mem_usage 391064 # Number of bytes of host memory used
|
|
|
|
host_seconds 42.12 # Real time elapsed on the host
|
2012-06-29 17:19:03 +02:00
|
|
|
sim_insts 90602407 # Number of instructions simulated
|
|
|
|
sim_ops 91252960 # Number of ops (including micro ops) simulated
|
2014-01-24 22:29:33 +01:00
|
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
2012-06-29 17:19:03 +02:00
|
|
|
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
|
|
|
|
system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
|
|
|
|
system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory
|
|
|
|
system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory
|
|
|
|
system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory
|
2012-06-05 07:23:16 +02:00
|
|
|
system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
|
|
|
|
system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
|
2012-06-29 17:19:03 +02:00
|
|
|
system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory
|
|
|
|
system.physmem.num_reads::cpu.data 22553294 # Number of read requests responded to by this memory
|
|
|
|
system.physmem.num_reads::total 130384064 # Number of read requests responded to by this memory
|
2012-06-05 07:23:16 +02:00
|
|
|
system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
|
|
|
|
system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
|
2012-06-29 17:19:03 +02:00
|
|
|
system.physmem.bw_read::cpu.inst 7952024773 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_read::cpu.data 1659577821 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_read::total 9611602595 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_inst_read::cpu.inst 7952024773 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_inst_read::total 7952024773 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_write::cpu.data 348597116 # Write bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_write::total 348597116 # Write bandwidth from this memory (bytes/s)
|
|
|
|
system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.throughput 9960199711 # Throughput (bytes/s)
|
|
|
|
system.membus.data_through_bus 540247816 # Total data (bytes)
|
|
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2010-11-08 20:58:25 +01:00
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2010-11-08 20:58:25 +01:00
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.numCycles 108481323 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.committedInsts 90602407 # Number of instructions committed
|
|
|
|
system.cpu.committedOps 91252960 # Number of ops (including micro ops) committed
|
|
|
|
system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.num_func_calls 112245 # number of times a function call or return occured
|
2012-09-25 18:49:41 +02:00
|
|
|
system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.num_int_insts 72525674 # number of integer instructions
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.num_fp_insts 48 # number of float instructions
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.num_int_register_reads 396967282 # number of times the integer registers were read
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
|
|
|
|
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.num_mem_refs 27318810 # number of memory refs
|
|
|
|
system.cpu.num_load_insts 22573966 # Number of load instructions
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_store_insts 4744844 # Number of store instructions
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.num_busy_cycles 108481323 # Number of busy cycles
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
2014-02-16 18:40:34 +01:00
|
|
|
system.cpu.Branches 18732304 # Number of branches fetched
|
2010-07-27 07:03:44 +02:00
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|