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gem5/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt

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Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- Begin Simulation Statistics ----------
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
sim_seconds 0.000473 # Number of seconds simulated
sim_ticks 473250000 # Number of ticks simulated
final_tick 473250000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
host_tick_rate 101630905 # Simulator tick rate (ticks/s)
host_mem_usage 277340 # Number of bytes of host memory used
host_seconds 4.66 # Real time elapsed on the host
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.physmem.bytes_read::cpu0 80424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 83171 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 80813 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 86214 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 79490 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 82665 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 85333 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 80902 # Number of bytes read from this memory
system.physmem.bytes_read::total 659012 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 419392 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5448 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5355 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5405 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5451 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5481 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5462 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5450 # Number of bytes written to this memory
system.physmem.bytes_written::total 462904 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 11061 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 10973 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 10946 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 11055 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 10883 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 10908 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 11056 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 10909 # Number of read requests responded to by this memory
system.physmem.num_reads::total 87791 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6553 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5448 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5355 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5405 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5451 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5481 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5462 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5450 # Number of write requests responded to by this memory
system.physmem.num_writes::total 50065 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 169939778 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 175744321 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 170761754 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 182174326 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 167966191 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 174675119 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 180312731 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 170949815 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1392524036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 886195457 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 11537242 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 11511886 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 11315372 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 11421025 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 11518225 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 11581616 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 11541469 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 11516112 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 978138405 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 886195457 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 181477021 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 187256207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 182077126 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 193595351 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 179484416 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 186256735 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 191854200 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 182465927 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2370662441 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu0.num_reads 98988 # number of read accesses completed
system.cpu0.num_writes 54550 # number of write accesses completed
system.cpu0.l1c.tags.replacements 22171 # number of replacements
system.cpu0.l1c.tags.tagsinuse 391.248330 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13318 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22569 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.590101 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu0.l1c.tags.occ_blocks::cpu0 391.248330 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.764157 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.764157 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 335805 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 335805 # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0 8501 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8501 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9644 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9644 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9644 # number of overall hits
system.cpu0.l1c.overall_hits::total 9644 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36474 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36474 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 23719 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 23719 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60193 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60193 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60193 # number of overall misses
system.cpu0.l1c.overall_misses::total 60193 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 587864141 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 587864141 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 652231215 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 652231215 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1240095356 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1240095356 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1240095356 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1240095356 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 44975 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 44975 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 24862 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 24862 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 69837 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 69837 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 69837 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 69837 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810984 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.810984 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954026 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.954026 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.861907 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.861907 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.861907 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.861907 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16117.347727 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 16117.347727 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27498.259412 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 27498.259412 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 20601.986211 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 20601.986211 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 20601.986211 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 20601.986211 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 773904 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu0.l1c.blocked::no_mshrs 66096 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.708787 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu0.l1c.writebacks::writebacks 9687 # number of writebacks
system.cpu0.l1c.writebacks::total 9687 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36474 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36474 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23719 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 23719 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60193 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60193 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60193 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60193 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 531003039 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 531003039 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 615653301 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 615653301 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1146656340 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1146656340 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1146656340 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1146656340 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 646054384 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 646054384 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 971060215 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 971060215 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1617114599 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1617114599 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810984 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810984 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954026 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954026 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.861907 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861907 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.861907 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14558.398832 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14558.398832 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25956.123825 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25956.123825 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu1.num_reads 99262 # number of read accesses completed
system.cpu1.num_writes 54743 # number of write accesses completed
system.cpu1.l1c.tags.replacements 22415 # number of replacements
system.cpu1.l1c.tags.tagsinuse 391.761420 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13414 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.587972 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu1.l1c.tags.occ_blocks::cpu1 391.761420 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.765159 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.765159 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 336589 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 336589 # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1 8598 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8598 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1162 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1162 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9760 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9760 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9760 # number of overall hits
system.cpu1.l1c.overall_hits::total 9760 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36477 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36477 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23776 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23776 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60253 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses
system.cpu1.l1c.overall_misses::total 60253 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 595460828 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 595460828 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 649149772 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 649149772 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1244610600 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1244610600 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1244610600 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1244610600 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 45075 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 45075 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 24938 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 24938 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 70013 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 70013 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 70013 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 70013 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809251 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.809251 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953404 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.953404 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.860597 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.860597 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.860597 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.860597 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16324.281821 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 16324.281821 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27302.732672 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 27302.732672 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 20656.408810 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 20656.408810 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 20656.408810 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 20656.408810 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 769857 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu1.l1c.blocked::no_mshrs 65915 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.679542 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu1.l1c.writebacks::writebacks 9826 # number of writebacks
system.cpu1.l1c.writebacks::total 9826 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36477 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23776 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23776 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 538442174 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 538442174 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 612498892 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 612498892 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1150941066 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1150941066 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1150941066 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1150941066 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 637533564 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 637533564 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 980538192 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 980538192 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1618071756 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1618071756 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809251 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809251 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953404 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953404 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.860597 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860597 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.860597 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14761.141925 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14761.141925 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25761.225269 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25761.225269 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu2.num_reads 99661 # number of read accesses completed
system.cpu2.num_writes 54617 # number of write accesses completed
system.cpu2.l1c.tags.replacements 22463 # number of replacements
system.cpu2.l1c.tags.tagsinuse 392.489979 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13594 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22875 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.594273 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu2.l1c.tags.occ_blocks::cpu2 392.489979 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.766582 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.766582 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 412 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.804688 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 338191 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 338191 # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2 8852 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8852 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1132 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1132 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9984 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9984 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9984 # number of overall hits
system.cpu2.l1c.overall_hits::total 9984 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36597 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36597 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 23791 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 23791 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 60388 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60388 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60388 # number of overall misses
system.cpu2.l1c.overall_misses::total 60388 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 596108462 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 596108462 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 646461820 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 646461820 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1242570282 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1242570282 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1242570282 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1242570282 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 45449 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 45449 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 24923 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 24923 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70372 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70372 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805232 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.805232 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954580 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.954580 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.858125 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.858125 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.858125 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.858125 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16288.451567 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 16288.451567 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27172.536674 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 27172.536674 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 20576.443697 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 20576.443697 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 20576.443697 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 20576.443697 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 768951 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu2.l1c.blocked::no_mshrs 65985 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.653421 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu2.l1c.writebacks::writebacks 9852 # number of writebacks
system.cpu2.l1c.writebacks::total 9852 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36597 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36597 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23791 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 23791 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 60388 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60388 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60388 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60388 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 538960044 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 538960044 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 609774472 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 609774472 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1148734516 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1148734516 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1148734516 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1148734516 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638400628 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638400628 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 959722740 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 959722740 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1598123368 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1598123368 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805232 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805232 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954580 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954580 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.858125 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858125 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.858125 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14726.891385 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14726.891385 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 25630.468328 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 25630.468328 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu3.num_reads 100000 # number of read accesses completed
system.cpu3.num_writes 55095 # number of write accesses completed
system.cpu3.l1c.tags.replacements 22209 # number of replacements
system.cpu3.l1c.tags.tagsinuse 391.627346 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13529 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 22601 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.598602 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu3.l1c.tags.occ_blocks::cpu3 391.627346 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.764897 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.764897 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 338542 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 338542 # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3 8783 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8783 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1149 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1149 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9932 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9932 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9932 # number of overall hits
system.cpu3.l1c.overall_hits::total 9932 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36678 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36678 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 23815 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 23815 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60493 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60493 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60493 # number of overall misses
system.cpu3.l1c.overall_misses::total 60493 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 595385248 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 595385248 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 651992109 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 651992109 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1247377357 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1247377357 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1247377357 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1247377357 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 45461 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 45461 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 24964 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70425 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70425 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70425 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70425 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806801 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.806801 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953974 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.953974 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.858971 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.858971 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.858971 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.858971 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16232.762092 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 16232.762092 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27377.371782 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 27377.371782 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 20620.193361 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 20620.193361 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 20620.193361 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 20620.193361 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 774947 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu3.l1c.blocked::no_mshrs 66468 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.658949 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu3.l1c.writebacks::writebacks 9869 # number of writebacks
system.cpu3.l1c.writebacks::total 9869 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36678 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36678 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23815 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60493 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60493 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60493 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60493 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 538014612 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 538014612 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 615289695 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 615289695 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1153304307 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1153304307 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1153304307 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1153304307 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 640462998 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 640462998 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962755753 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962755753 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1603218751 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1603218751 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806801 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806801 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953974 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.858971 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858971 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.858971 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14668.591853 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14668.591853 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25836.224858 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25836.224858 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19065.086985 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu4.num_reads 99958 # number of read accesses completed
system.cpu4.num_writes 55186 # number of write accesses completed
system.cpu4.l1c.tags.replacements 22162 # number of replacements
system.cpu4.l1c.tags.tagsinuse 390.917230 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13739 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22564 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.608890 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu4.l1c.tags.occ_blocks::cpu4 390.917230 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.763510 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.763510 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 338274 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 338274 # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4 8951 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8951 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1108 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1108 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 10059 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 10059 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 10059 # number of overall hits
system.cpu4.l1c.overall_hits::total 10059 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36463 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36463 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23892 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23892 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 60355 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 60355 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 60355 # number of overall misses
system.cpu4.l1c.overall_misses::total 60355 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 590532010 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 590532010 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 657391664 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 657391664 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1247923674 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1247923674 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1247923674 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1247923674 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 45414 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 45414 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 25000 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 25000 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 70414 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 70414 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 70414 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 70414 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.802902 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.802902 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955680 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.955680 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.857145 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.857145 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.857145 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.857145 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16195.376409 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 16195.376409 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27515.137452 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 27515.137452 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 20676.392577 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 20676.392577 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 20676.392577 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 20676.392577 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 772044 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu4.l1c.blocked::no_mshrs 66046 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.689489 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu4.l1c.writebacks::writebacks 9680 # number of writebacks
system.cpu4.l1c.writebacks::total 9680 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36463 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36463 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23892 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23892 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 60355 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 60355 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 60355 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 60355 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 533535272 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 533535272 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 620520370 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 620520370 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1154055642 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1154055642 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1154055642 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1154055642 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 636776082 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 636776082 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 976656146 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 976656146 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1613432228 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1613432228 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.802902 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.802902 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955680 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955680 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857145 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.857145 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857145 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.857145 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14632.237391 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14632.237391 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25971.888917 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25971.888917 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu5.num_reads 98793 # number of read accesses completed
system.cpu5.num_writes 54966 # number of write accesses completed
system.cpu5.l1c.tags.replacements 22337 # number of replacements
system.cpu5.l1c.tags.tagsinuse 392.447401 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13310 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 22755 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.584926 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu5.l1c.tags.occ_blocks::cpu5 392.447401 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.766499 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 335862 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 335862 # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5 8554 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8554 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1127 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1127 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 9681 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9681 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9681 # number of overall hits
system.cpu5.l1c.overall_hits::total 9681 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36144 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36144 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 24019 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 24019 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 60163 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 60163 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 60163 # number of overall misses
system.cpu5.l1c.overall_misses::total 60163 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 586243376 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 586243376 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 664085386 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 664085386 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1250328762 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1250328762 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1250328762 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1250328762 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 44698 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 44698 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 25146 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 25146 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 69844 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 69844 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 69844 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 69844 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808627 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.808627 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955182 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.955182 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.861391 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.861391 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.861391 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.861391 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16219.659584 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 16219.659584 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27648.336151 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 27648.336151 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 20782.353972 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 20782.353972 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 20782.353972 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 20782.353972 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 771700 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu5.l1c.blocked::no_mshrs 65809 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.726360 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu5.l1c.writebacks::writebacks 9916 # number of writebacks
system.cpu5.l1c.writebacks::total 9916 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36144 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24019 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 24019 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 60163 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 60163 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 60163 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 60163 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 529678552 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 529678552 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 626959212 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 626959212 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156637764 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1156637764 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156637764 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1156637764 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 632837521 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 632837521 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 970316626 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 970316626 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1603154147 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1603154147 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808627 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808627 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955182 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955182 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.861391 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861391 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.861391 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14654.674413 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14654.674413 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26102.635913 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26102.635913 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19225.067965 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19225.067965 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu6.num_reads 99383 # number of read accesses completed
system.cpu6.num_writes 54752 # number of write accesses completed
system.cpu6.l1c.tags.replacements 22371 # number of replacements
system.cpu6.l1c.tags.tagsinuse 391.299314 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13429 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.589975 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu6.l1c.tags.occ_blocks::cpu6 391.299314 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.764256 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.764256 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 336995 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 336995 # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1088 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1088 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9819 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9819 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9819 # number of overall hits
system.cpu6.l1c.overall_hits::total 9819 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36545 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36545 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 23737 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 23737 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60282 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60282 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60282 # number of overall misses
system.cpu6.l1c.overall_misses::total 60282 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 590611551 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 590611551 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 651380889 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 651380889 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1241992440 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1241992440 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1241992440 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1241992440 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45276 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45276 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 24825 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 24825 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70101 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70101 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70101 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70101 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807161 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.807161 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956173 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.956173 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.859931 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.859931 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.859931 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.859931 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16161.213600 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 16161.213600 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27441.584404 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 27441.584404 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 20603.039713 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 20603.039713 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 20603.039713 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 20603.039713 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 771561 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu6.l1c.blocked::no_mshrs 66088 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.674752 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu6.l1c.writebacks::writebacks 9782 # number of writebacks
system.cpu6.l1c.writebacks::total 9782 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36545 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36545 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23737 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 23737 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60282 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60282 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60282 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60282 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 533644023 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 533644023 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 614831387 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 614831387 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1148475410 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1148475410 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148475410 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1148475410 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 641180935 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 641180935 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 971245186 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 971245186 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1612426121 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1612426121 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807161 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807161 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956173 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956173 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.859931 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859931 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.859931 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14602.381256 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14602.381256 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25901.815183 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25901.815183 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19051.713779 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19051.713779 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu7.num_reads 99477 # number of read accesses completed
system.cpu7.num_writes 54915 # number of write accesses completed
system.cpu7.l1c.tags.replacements 22352 # number of replacements
system.cpu7.l1c.tags.tagsinuse 391.525005 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13561 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22758 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.595878 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu7.l1c.tags.occ_blocks::cpu7 391.525005 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.764697 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.764697 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 337629 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 337629 # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7 8790 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8790 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1137 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1137 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 9927 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9927 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9927 # number of overall hits
system.cpu7.l1c.overall_hits::total 9927 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36477 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36477 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23844 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23844 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60321 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60321 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60321 # number of overall misses
system.cpu7.l1c.overall_misses::total 60321 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 593716610 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 593716610 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 651325348 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 651325348 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1245041958 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1245041958 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1245041958 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1245041958 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 45267 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 45267 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 24981 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 24981 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 70248 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 70248 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 70248 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 70248 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805819 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.805819 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954485 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.954485 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.858686 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.858686 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.858686 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.858686 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16276.464896 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 16276.464896 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27316.110887 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 27316.110887 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 20640.273835 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 20640.273835 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 20640.273835 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 20640.273835 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 768557 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu7.l1c.blocked::no_mshrs 65923 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.658405 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu7.l1c.writebacks::writebacks 9939 # number of writebacks
system.cpu7.l1c.writebacks::total 9939 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36477 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36477 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23844 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23844 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60321 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60321 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60321 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 536729312 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 536729312 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 614614324 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 614614324 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1151343636 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1151343636 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1151343636 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1151343636 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 635643033 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 635643033 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 965131654 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 965131654 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1600774687 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1600774687 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805819 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805819 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954485 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954485 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.858686 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858686 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.858686 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14714.184609 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14714.184609 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25776.477269 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25776.477269 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19086.945442 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19086.945442 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.tags.replacements 13851 # number of replacements
system.l2c.tags.tagsinuse 783.697862 # Cycle average of tags in use
system.l2c.tags.total_refs 151322 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 14625 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 10.346803 # Average number of references to valid blocks.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.tags.occ_blocks::writebacks 724.401984 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 7.094586 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 7.546674 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 7.606935 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 7.397120 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 7.288170 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 7.917650 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 7.470007 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 6.974735 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.707424 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.006928 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.007370 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.007429 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.007224 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.007117 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.007732 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.007295 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.006811 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.765330 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 774 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 649 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 1983958 # Number of tag accesses
system.l2c.tags.data_accesses 1983958 # Number of data accesses
system.l2c.ReadReq_hits::cpu0 10711 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1 10778 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2 10851 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3 10748 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4 10782 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5 10733 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6 10660 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7 10974 # number of ReadReq hits
system.l2c.ReadReq_hits::total 86237 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 76857 # number of Writeback hits
system.l2c.Writeback_hits::total 76857 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0 346 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 384 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 373 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 367 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 376 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 343 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 335 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2885 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1899 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1990 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1993 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1893 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 2001 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 2049 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1965 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1890 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 15680 # number of ReadExReq hits
system.l2c.demand_hits::cpu0 12610 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12768 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12844 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12641 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12783 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12782 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12625 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12864 # number of demand (read+write) hits
system.l2c.demand_hits::total 101917 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12610 # number of overall hits
system.l2c.overall_hits::cpu1 12768 # number of overall hits
system.l2c.overall_hits::cpu2 12844 # number of overall hits
system.l2c.overall_hits::cpu3 12641 # number of overall hits
system.l2c.overall_hits::cpu4 12783 # number of overall hits
system.l2c.overall_hits::cpu5 12782 # number of overall hits
system.l2c.overall_hits::cpu6 12625 # number of overall hits
system.l2c.overall_hits::cpu7 12864 # number of overall hits
system.l2c.overall_hits::total 101917 # number of overall hits
system.l2c.ReadReq_misses::cpu0 698 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1 756 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2 731 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3 765 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4 706 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5 759 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6 730 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7 718 # number of ReadReq misses
system.l2c.ReadReq_misses::total 5863 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0 1969 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 1976 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 1906 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 1935 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 2000 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 2012 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 1921 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 15706 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4442 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4288 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4325 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4406 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4415 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4506 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4417 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4371 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 35170 # number of ReadExReq misses
system.l2c.demand_misses::cpu0 5140 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 5044 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5056 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 5171 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5121 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5265 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 5147 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5089 # number of demand (read+write) misses
system.l2c.demand_misses::total 41033 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 5140 # number of overall misses
system.l2c.overall_misses::cpu1 5044 # number of overall misses
system.l2c.overall_misses::cpu2 5056 # number of overall misses
system.l2c.overall_misses::cpu3 5171 # number of overall misses
system.l2c.overall_misses::cpu4 5121 # number of overall misses
system.l2c.overall_misses::cpu5 5265 # number of overall misses
system.l2c.overall_misses::cpu6 5147 # number of overall misses
system.l2c.overall_misses::cpu7 5089 # number of overall misses
system.l2c.overall_misses::total 41033 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0 43733919 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1 46361427 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2 45254929 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3 46924929 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4 44013419 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5 46972420 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6 45169428 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7 45070420 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 363500891 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0 59896998 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 56953495 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 54104996 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 56752496 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 58374994 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 58176496 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 54809998 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 58271994 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 457341467 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 244729947 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 236328444 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 237901947 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 242524942 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 242982942 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 248203441 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 243651932 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 239891953 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1936215548 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0 288463866 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 282689871 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 283156876 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 289449871 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 286996361 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 295175861 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 288821360 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 284962373 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2299716439 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 288463866 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 282689871 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 283156876 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 289449871 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 286996361 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 295175861 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 288821360 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 284962373 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2299716439 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0 11409 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1 11534 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2 11582 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3 11513 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4 11488 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5 11492 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6 11390 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7 11692 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 92100 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 76857 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 76857 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2315 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2360 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2279 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2302 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2376 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2355 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2322 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18591 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6341 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6278 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6318 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6299 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6416 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6555 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6382 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6261 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 50850 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 17750 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 17812 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 17900 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 17812 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 17904 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 18047 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 17772 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 17953 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 142950 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 17750 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 17812 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 17900 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 17812 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 17904 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 18047 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 17772 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 17953 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 142950 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0 0.061180 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1 0.065545 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2 0.063115 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3 0.066447 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4 0.061455 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5 0.066046 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6 0.064091 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7 0.061410 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.063659 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.850540 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.837288 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.836332 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.840573 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.841751 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.854352 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.841805 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.855728 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.844817 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.700520 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.683020 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.684552 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.699476 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.688123 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.687414 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.692103 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.698131 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.691642 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0 0.289577 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.283180 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.282458 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.290310 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.286025 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.291738 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.289613 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.283462 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.287044 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.289577 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.283180 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.282458 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.290310 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.286025 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.291738 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.289613 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.283462 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.287044 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 62656.044413 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 61324.638889 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 61908.247606 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 61339.776471 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 62341.953258 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 61887.246377 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 61875.928767 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 62772.172702 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 61999.128603 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 30420.009142 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 28822.618927 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 28386.671563 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 29329.455297 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 29187.497000 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 28914.759443 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 28532.013535 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 29326.620030 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 29118.901503 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 55094.540072 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 55113.909515 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 55006.230520 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 55044.244666 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 55035.773952 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 55082.876387 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 55162.311976 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 54882.624800 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 55053.043730 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 56121.374708 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 56044.780135 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 56004.128956 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 55975.608393 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 56043.030853 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 56063.791263 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 56114.505537 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 55995.750246 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 56045.535033 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 56121.374708 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 56044.780135 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 56004.128956 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 55975.608393 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 56043.030853 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 56063.791263 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 56114.505537 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 55995.750246 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 56045.535033 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 17878 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.blocked::no_mshrs 3319 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.avg_blocked_cycles::no_mshrs 5.386562 # average number of cycles each access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.writebacks::writebacks 6553 # number of writebacks
system.l2c.writebacks::total 6553 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1 8 # number of ReadReq MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5 11 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2 7 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3 7 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 48 # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 15 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 13 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 20 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 13 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 15 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 13 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 20 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 13 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 108 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0 690 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1 748 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2 723 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3 759 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4 699 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5 748 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6 725 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7 711 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 5803 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 1969 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 1976 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 1906 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 1935 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 1999 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 2012 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 1921 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 1986 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 15704 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4438 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4282 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4318 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4399 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4410 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4497 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4413 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4365 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 35122 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 5128 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 5030 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5041 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 5158 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5109 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5245 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 5138 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5076 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 40925 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 5128 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 5030 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5041 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 5158 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5109 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5245 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 5138 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5076 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 40925 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0 35173417 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1 37031918 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2 36254417 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3 37641417 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4 35371412 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5 37570056 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6 36289420 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7 36247403 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 291579460 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 83090959 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 83391451 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80567464 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 81939961 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 84801962 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 85113946 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 81126982 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 83903452 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 663936177 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 190977391 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 184459864 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 185520379 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 189280870 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 189565364 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 193586876 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 190188358 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 187005383 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1510584485 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 226150808 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 221491782 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 221774796 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 226922287 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 224936776 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 231156932 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 226477778 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 223252786 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1802163945 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 226150808 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 221491782 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 221774796 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 226922287 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 224936776 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 231156932 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 226477778 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 223252786 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1802163945 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 423951568 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 418494765 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 418742272 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 420173606 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 417698791 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 416045242 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 420505761 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 416931790 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3352543795 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 241936896 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 242321875 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 237941390 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 239219888 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 241365909 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 242888399 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 243671384 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 242767880 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1932113621 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 665888464 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 660816640 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 656683662 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 659393494 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 659064700 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 658933641 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 664177145 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 659699670 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 5284657416 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0 0.060479 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064852 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062424 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3 0.065925 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060846 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5 0.065089 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063652 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060811 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.063008 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.850540 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.837288 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.836332 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.840573 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.841330 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.854352 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841805 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.855297 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.844710 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.699890 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682064 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.683444 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.698365 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687344 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.686041 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.691476 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.697173 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.690698 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.286289 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.286289 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50975.966667 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49507.911765 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50144.421853 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49593.434783 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50602.878398 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.347594 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50054.372414 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50980.876231 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 50246.331208 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42199.572880 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42202.151316 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42270.442812 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42346.233075 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42422.192096 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42303.154076 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42231.640812 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42247.458207 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42278.156966 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43032.309824 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43077.969173 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42964.423113 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43028.158672 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42985.343311 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43048.004447 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43097.293904 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42842.012142 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 43009.637407 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.membus.trans_dist::ReadReq 84510 # Transaction distribution
system.membus.trans_dist::ReadResp 84504 # Transaction distribution
system.membus.trans_dist::WriteReq 43512 # Transaction distribution
system.membus.trans_dist::WriteResp 43509 # Transaction distribution
system.membus.trans_dist::Writeback 6553 # Transaction distribution
system.membus.trans_dist::UpgradeReq 58529 # Transaction distribution
system.membus.trans_dist::UpgradeResp 47554 # Transaction distribution
system.membus.trans_dist::ReadExReq 49190 # Transaction distribution
system.membus.trans_dist::ReadExResp 3281 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421142 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 421142 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1121847 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1121847 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 56880 # Total snoops (count)
system.membus.snoop_fanout::samples 123632 # Request fanout histogram
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.membus.snoop_fanout::0 123632 100.00% 100.00% # Request fanout histogram
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.membus.snoop_fanout::total 123632 # Request fanout histogram
system.membus.reqLayer0.occupancy 285799779 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 60.4 # Layer utilization (%)
system.membus.respLayer0.occupancy 306149550 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 64.7 # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq 370575 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 370557 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 7 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43514 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43509 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 76857 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 29562 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 29559 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 161030 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 161024 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120575 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120590 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120586 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120766 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120839 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 965293 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1758906 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1769834 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1777815 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1771618 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1766732 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791122 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1765164 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788112 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 14189303 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 320901 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 563826 # Request fanout histogram
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.toL2Bus.snoop_fanout::7 563826 100.00% 100.00% # Request fanout histogram
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.toL2Bus.snoop_fanout::total 563826 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 445759226 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 94.2 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 101149991 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%)
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.toL2Bus.respLayer1.occupancy 101191512 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%)
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.toL2Bus.respLayer2.occupancy 101359906 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%)
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.toL2Bus.respLayer3.occupancy 101648274 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 21.5 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 101307289 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%)
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.toL2Bus.respLayer5.occupancy 101134998 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 21.4 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 101213033 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 21.4 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 101242964 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%)
Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- End Simulation Statistics ----------
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