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gem5/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt

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config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
---------- Begin Simulation Statistics ----------
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
sim_seconds 0.133779 # Number of seconds simulated
sim_ticks 133778696500 # Number of ticks simulated
final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
host_inst_rate 208111 # Simulator instruction rate (inst/s)
host_op_rate 208111 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49227708 # Simulator tick rate (ticks/s)
host_mem_usage 215496 # Number of bytes of host memory used
host_seconds 2717.55 # Real time elapsed on the host
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
sim_insts 565552443 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 565552443 # Number of ops (including micro ops) simulated
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1636416 # Number of bytes read from this memory
system.physmem.bytes_read::total 1697280 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67008 # Number of bytes written to this memory
system.physmem.bytes_written::total 67008 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25569 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26520 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1047 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1047 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 454960 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12232262 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12687222 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 454960 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 454960 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 500887 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 500887 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 500887 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 454960 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12232262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13188109 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26520 # Total number of read requests seen
system.physmem.writeReqs 1047 # Total number of write requests seen
system.physmem.cpureqs 27567 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1697280 # Total number of bytes read from memory
system.physmem.bytesWritten 67008 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1697280 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 67008 # bytesWritten derated as per pkt->getSize()
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::1 1736 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1612 # Track reads on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::5 1642 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1685 # Track reads on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::8 1568 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1629 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1615 # Track reads on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::12 1668 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1651 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1704 # Track reads on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 55 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 84 # Track writes on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankWrReqs::10 57 # Track writes on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankWrReqs::12 64 # Track writes on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankWrReqs::14 78 # Track writes on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.totGap 133778628000 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.readPktSize::6 26520 # Categorize read packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.writePktSize::6 1047 # categorize write packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::0 10090 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 10502 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 4903 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.totQLat 650833420 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1266537420 # Sum of mem lat for all requests
system.physmem.totBusLat 106020000 # Total cycles spent in databus access
system.physmem.totBankLat 509684000 # Total cycles spent in bank access
system.physmem.avgQLat 24555.12 # Average queueing delay per request
system.physmem.avgBankLat 19229.73 # Average bank access latency per request
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgBusLat 4000.00 # Average bus latency per request
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.avgMemAccLat 47784.85 # Average memory access latency
system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.08 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.avgWrQLen 10.37 # Average write queue length over time
system.physmem.readRowHits 18044 # Number of row buffer hits during reads
system.physmem.writeRowHits 53 # Number of row buffer hits during writes
system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes
system.physmem.avgGap 4852854.06 # Average gap between requests
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.read_hits 122603551 # DTB read hits
system.cpu.dtb.read_misses 28565 # DTB read misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.read_accesses 122632116 # DTB read accesses
system.cpu.dtb.write_hits 40753368 # DTB write hits
system.cpu.dtb.write_misses 25574 # DTB write misses
StoreSet: Update stats for store-set clearing
2011-08-19 22:08:08 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.write_accesses 40778942 # DTB write accesses
system.cpu.dtb.data_hits 163356919 # DTB hits
system.cpu.dtb.data_misses 54139 # DTB misses
StoreSet: Update stats for store-set clearing
2011-08-19 22:08:08 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.data_accesses 163411058 # DTB accesses
system.cpu.itb.fetch_hits 65475592 # ITB hits
system.cpu.itb.fetch_misses 42 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.itb.fetch_accesses 65475634 # ITB accesses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.numCycles 267557394 # number of cpu cycles simulated
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.BPredUnit.lookups 76440222 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 70864810 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2706098 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 43060392 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 41933015 # Number of BTB hits
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.BPredUnit.usedRAS 1604413 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed
system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 43537428 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 117782486 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 11617306 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 73490715 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1303 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 65475592 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 928038 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 267274328 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.615488 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.444547 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.fetch.rateDist::0 149491842 55.93% 55.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 10342090 3.87% 59.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 11847639 4.43% 64.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 10563390 3.95% 68.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 7011808 2.62% 70.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2869024 1.07% 71.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3576964 1.34% 73.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3101400 1.16% 74.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 68470171 25.62% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.fetch.rateDist::total 267274328 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.285697 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.612721 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 84240613 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 57793701 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 102635866 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 13724657 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 8879491 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3873839 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 920 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 691093913 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3105 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 8879491 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 92211740 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 12790279 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1241 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 103054645 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 50336932 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 680961604 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 408 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 38688874 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 5430085 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 520709674 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 896990234 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 896987596 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2638 # Number of floating rename lookups
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.rename.UndoneMaps 56854785 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 64 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 69 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 112289485 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 126970724 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 42377686 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 14852387 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 10147583 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 621083354 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 604563100 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 299815 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 54897951 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 29938787 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 267274328 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.261957 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.823661 # Number of insts issued each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.issued_per_cycle::0 52499760 19.64% 19.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 55875325 20.91% 40.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 53442699 20.00% 60.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 36269586 13.57% 74.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 31423380 11.76% 85.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 23799839 8.90% 94.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 9996979 3.74% 98.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3415050 1.28% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 551710 0.21% 100.00% # Number of insts issued each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.issued_per_cycle::total 267274328 # Number of insts issued each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.fu_full::IntAlu 2734710 70.93% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 35 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 729519 18.92% 89.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 391400 10.15% 100.00% # attempts to use FU when none available
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::IntAlu 439055623 72.62% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 7072 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 124323040 20.56% 93.19% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 41177317 6.81% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::total 604563100 # Type of FU issued
system.cpu.iq.rate 2.259564 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3855664 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006378 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1480552206 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 675984537 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 596489873 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3801 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2284 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1738 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 608416848 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1916 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 12282855 # Number of loads that had data forwarded from stores
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 12456682 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 35904 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 5518 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2926365 # Number of stores squashed
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 6461 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 52889 # Number of times an access to memory failed due to the cache being blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.iewSquashCycles 8879491 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1456554 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 192142 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 663913486 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1691538 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 126970724 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 42377686 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 144242 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 7408 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 5518 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1333964 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1804152 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3138116 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 599464075 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 122632263 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 5099025 # Number of squashed instructions skipped in execute
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.exec_nop 42830076 # number of nop insts executed
system.cpu.iew.exec_refs 163429760 # number of memory reference insts executed
system.cpu.iew.exec_branches 66623337 # Number of branches executed
system.cpu.iew.exec_stores 40797497 # Number of stores executed
system.cpu.iew.exec_rate 2.240506 # Inst execution rate
system.cpu.iew.wb_sent 597426155 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 596491611 # cumulative count of insts written-back
system.cpu.iew.wb_producers 415927297 # num instructions producing a value
system.cpu.iew.wb_consumers 530215795 # num instructions consuming a value
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.wb_rate 2.229397 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.784449 # average fanout of values written-back
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.commitSquashedInsts 61932723 # The number of squashed insts skipped by commit
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.branchMispredicts 2705240 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 258394837 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.329214 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.691172 # Number of insts commited each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.committed_per_cycle::0 79550578 30.79% 30.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 72525012 28.07% 58.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 25515345 9.87% 68.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 9289171 3.59% 72.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 10288497 3.98% 76.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 21029047 8.14% 84.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 6874256 2.66% 87.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3694459 1.43% 88.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 29628472 11.47% 100.00% # Number of insts commited each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.committed_per_cycle::total 258394837 # Number of insts commited each cycle
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 153965363 # Number of memory references committed
system.cpu.commit.loads 114514042 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 62547159 # Number of branches committed
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.bw_lim_events 29628472 # number cycles where commit BW limit reached
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.rob.rob_reads 892491662 # The number of ROB reads
system.cpu.rob.rob_writes 1336472901 # The number of ROB writes
system.cpu.timesIdled 34286 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 283066 # Total number of cycles that the CPU has spent unscheduled due to idling
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.cpi 0.473090 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.473090 # CPI: Total CPI of All Threads
system.cpu.ipc 2.113761 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.113761 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 844970192 # number of integer regfile reads
system.cpu.int_regfile_writes 490533624 # number of integer regfile writes
system.cpu.fp_regfile_reads 397 # number of floating regfile reads
system.cpu.fp_regfile_writes 54 # number of floating regfile writes
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.replacements 36 # number of replacements
system.cpu.icache.tagsinuse 825.012562 # Cycle average of tags in use
system.cpu.icache.total_refs 65474211 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 67848.923316 # Average number of references to valid blocks.
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.occ_blocks::cpu.inst 825.012562 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.402838 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.402838 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 65474211 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 65474211 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 65474211 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 65474211 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 65474211 # number of overall hits
system.cpu.icache.overall_hits::total 65474211 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses
system.cpu.icache.overall_misses::total 1381 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 68875500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 68875500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 68875500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 68875500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 68875500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 68875500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 65475592 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 65475592 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 65475592 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 65475592 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 65475592 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 65475592 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.642288 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49873.642288 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49873.642288 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49873.642288 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 416 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 416 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 416 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 416 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 416 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 416 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50216500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 50216500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50216500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 50216500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50216500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 50216500 # number of overall MSHR miss cycles
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52037.823834 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52037.823834 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52037.823834 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52037.823834 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52037.823834 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52037.823834 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.replacements 1079 # number of replacements
system.cpu.l2cache.tagsinuse 22916.104559 # Cycle average of tags in use
system.cpu.l2cache.total_refs 547186 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23511 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.273617 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21469.480813 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 814.509586 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 632.114161 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.655197 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.024857 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019291 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.699344 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 206252 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 206266 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 445099 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 445099 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 233316 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 233316 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 439568 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 439582 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 439568 # number of overall hits
system.cpu.l2cache.overall_hits::total 439582 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 951 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4308 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5259 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21261 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21261 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 951 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 25569 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26520 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 951 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 25569 # number of overall misses
system.cpu.l2cache.overall_misses::total 26520 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49100500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 424904500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 474005000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1450819500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1450819500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 49100500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1875724000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1924824500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 49100500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1875724000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1924824500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 210560 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 211525 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 445099 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 445099 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254577 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254577 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 465137 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 466102 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 465137 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 466102 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985492 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020460 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024862 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083515 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083515 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985492 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.054971 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.056897 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985492 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.054971 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.056897 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51630.389064 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 98631.499536 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 90132.154402 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68238.535346 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68238.535346 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51630.389064 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73359.302280 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72580.109351 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51630.389064 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73359.302280 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72580.109351 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1047 # number of writebacks
system.cpu.l2cache.writebacks::total 1047 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 951 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4308 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5259 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21261 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21261 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 951 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25569 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26520 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 951 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25569 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26520 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37144486 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 369346804 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 406491290 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1184806153 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1184806153 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37144486 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1554152957 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1591297443 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37144486 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1554152957 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1591297443 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985492 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020460 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024862 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083515 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083515 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985492 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054971 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.056897 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985492 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054971 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.056897 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39058.344900 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85735.098422 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77294.407682 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55726.736889 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55726.736889 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60782.703938 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60003.674321 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60782.703938 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60003.674321 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 461041 # number of replacements
system.cpu.dcache.tagsinuse 4090.869171 # Cycle average of tags in use
system.cpu.dcache.total_refs 146891319 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 465137 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 315.802267 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 305775000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4090.869171 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998747 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998747 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 109242892 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 109242892 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 37648409 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 37648409 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 146891301 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 146891301 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 146891301 # number of overall hits
system.cpu.dcache.overall_hits::total 146891301 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1026587 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1026587 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1802912 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1802912 # number of WriteReq misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.demand_misses::cpu.data 2829499 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2829499 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2829499 # number of overall misses
system.cpu.dcache.overall_misses::total 2829499 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15441177000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 15441177000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25867331616 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 25867331616 # number of WriteReq miss cycles
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 41308508616 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 41308508616 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 41308508616 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 41308508616 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 110269479 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 110269479 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 149720800 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 149720800 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 149720800 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 149720800 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.142857 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.142857 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.018899 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.018899 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.018899 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.018899 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15041.274631 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15041.274631 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14347.528674 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14347.528674 # average WriteReq miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9500 # average LoadLockedReq miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14599.230682 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14599.230682 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 277266 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 17305 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.022306 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 83.545455 # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.writebacks::writebacks 445099 # number of writebacks
system.cpu.dcache.writebacks::total 445099 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 816026 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 816026 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548336 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1548336 # number of WriteReq MSHR hits
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 2364362 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2364362 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2364362 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2364362 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210561 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 210561 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254576 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 254576 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 465137 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 465137 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 465137 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 465137 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2703972000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2703972000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4046409990 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4046409990 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6750381990 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6750381990 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6750381990 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6750381990 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003107 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003107 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12841.751321 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12841.751321 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15894.703311 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15894.703311 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink