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gem5/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt

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ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
sim_seconds 0.000115 # Number of seconds simulated
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_ticks 115089 # Number of ticks simulated
final_tick 115089 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
sim_freq 1000000000 # Frequency of simulated ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
host_inst_rate 64252 # Simulator instruction rate (inst/s)
host_op_rate 64242 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1314462 # Simulator tick rate (ticks/s)
host_mem_usage 449728 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94080 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 94080 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93824 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 93824 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.bw_read::ruby.dir_cntrl0 817454318 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 817454318 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 815229952 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 815229952 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1632684270 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 1632684270 # Total bandwidth to/from this memory (bytes/s)
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.readReqs 1470 # Number of read requests accepted
system.mem_ctrls.writeReqs 1466 # Number of write requests accepted
system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.bytesReadDRAM 58496 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 35584 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 59392 # Total number of bytes written to DRAM
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.servicedByWrQ 556 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 513 # Number of DRAM write bursts merged with an existing one
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankRdBursts::0 32 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 78 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 64 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 241 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 44 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 115 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 43 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 165 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 33 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankWrBursts::6 11 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 245 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 98 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 186 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.totGap 115018 # Total gap between requests
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1470 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.rdQLenPdf::0 914 # What read queue length does an incoming req see
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.wrQLenPdf::15 11 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 15 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 61 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 58 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.wrQLenPdf::21 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.bytesPerActivate::samples 343 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 339.965015 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 217.922152 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 320.777927 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 88 25.66% 25.66% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 98 28.57% 54.23% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 42 12.24% 66.47% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 32 9.33% 75.80% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 16 4.66% 80.47% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 13 3.79% 84.26% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 8 2.33% 86.59% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 5 1.46% 88.05% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 41 11.95% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 343 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 56 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 16.125000 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 15.967614 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 2.737368 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 2 3.57% 3.57% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 19 33.93% 37.50% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 27 48.21% 85.71% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 7 12.50% 98.21% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::34-35 1 1.79% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 56 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 56 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.571429 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.541189 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 1.041976 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 41 73.21% 73.21% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::17 3 5.36% 78.57% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 8 14.29% 92.86% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 3 5.36% 98.21% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::20 1 1.79% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 56 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 12397 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 29763 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 4570 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 13.56 # Average queueing delay per DRAM burst
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.avgMemAccLat 32.56 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 508.27 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 516.05 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 817.45 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 815.23 # Average system write bandwidth in MiByte/s
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.busUtil 8.00 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 3.97 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 4.03 # Data bus utilization in percentage for writes
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.avgWrQLen 25.10 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 631 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 861 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 69.04 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 90.35 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 39.18 # Average gap between requests
system.mem_ctrls.pageHitRate 79.91 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 544320 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 302400 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 1522560 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 1202688 # Energy for write commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_0.actBackEnergy 49529808 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 22111200 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 82332816 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 753.521892 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 36376 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_0.memoryStateTime::ACT 69262 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_1.actEnergy 1988280 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 1104600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 9397440 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 8076672 # Energy for write commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_1.actBackEnergy 74119608 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 541200 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 102347640 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 936.700469 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 1449 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_1.memoryStateTime::ACT 105142 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.clk_domain.clock 1 # Clock period in ticks
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.dtb.read_accesses 0 # DTB read accesses
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.workload.num_syscalls 7 # Number of system calls
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.numCycles 115089 # number of cpu cycles simulated
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.num_fp_insts 2 # number of float instructions
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.num_idle_cycles 0 # Number of idle cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.num_busy_cycles 115089 # Number of busy cycles
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 10:35:05 +02:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.op_class::total 5625 # Class of executed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 2936 # delay histogram for all message
system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 2936 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
system.ruby.outstanding_req_hist::samples 7659
system.ruby.outstanding_req_hist::mean 1
system.ruby.outstanding_req_hist::gmean 1
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist::total 7659
system.ruby.latency_hist::bucket_size 64
system.ruby.latency_hist::max_bucket 639
system.ruby.latency_hist::samples 7658
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.latency_hist::mean 14.028598
system.ruby.latency_hist::gmean 5.234161
system.ruby.latency_hist::stdev 27.167008
system.ruby.latency_hist | 7344 95.90% 95.90% | 261 3.41% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 9 0.12% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.latency_hist::total 7658
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
system.ruby.hit_latency_hist::samples 6188
system.ruby.hit_latency_hist::mean 3
system.ruby.hit_latency_hist::gmean 3.000000
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist::total 6188
system.ruby.miss_latency_hist::bucket_size 64
system.ruby.miss_latency_hist::max_bucket 639
system.ruby.miss_latency_hist::samples 1470
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.miss_latency_hist::mean 60.453741
system.ruby.miss_latency_hist::gmean 54.500138
system.ruby.miss_latency_hist::stdev 34.320124
system.ruby.miss_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.miss_latency_hist::total 1470
system.ruby.Directory.incomplete_times 1469
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers0.percent_links_utilized 6.377673
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.network.routers0.msg_count.Control::2 1470
system.ruby.network.routers0.msg_count.Data::2 1466
system.ruby.network.routers0.msg_count.Response_Data::4 1470
system.ruby.network.routers0.msg_count.Writeback_Control::3 1466
system.ruby.network.routers0.msg_bytes.Control::2 11760
system.ruby.network.routers0.msg_bytes.Data::2 105552
system.ruby.network.routers0.msg_bytes.Response_Data::4 105840
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers1.percent_links_utilized 6.377673
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.network.routers1.msg_count.Control::2 1470
system.ruby.network.routers1.msg_count.Data::2 1466
system.ruby.network.routers1.msg_count.Response_Data::4 1470
system.ruby.network.routers1.msg_count.Writeback_Control::3 1466
system.ruby.network.routers1.msg_bytes.Control::2 11760
system.ruby.network.routers1.msg_bytes.Data::2 105552
system.ruby.network.routers1.msg_bytes.Response_Data::4 105840
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers2.percent_links_utilized 6.377673
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.network.routers2.msg_count.Control::2 1470
system.ruby.network.routers2.msg_count.Data::2 1466
system.ruby.network.routers2.msg_count.Response_Data::4 1470
system.ruby.network.routers2.msg_count.Writeback_Control::3 1466
system.ruby.network.routers2.msg_bytes.Control::2 11760
system.ruby.network.routers2.msg_bytes.Data::2 105552
system.ruby.network.routers2.msg_bytes.Response_Data::4 105840
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728
system.ruby.network.msg_count.Control 4410
system.ruby.network.msg_count.Data 4398
system.ruby.network.msg_count.Response_Data 4410
system.ruby.network.msg_count.Writeback_Control 4398
system.ruby.network.msg_byte.Control 35280
system.ruby.network.msg_byte.Data 316656
system.ruby.network.msg_byte.Response_Data 317520
system.ruby.network.msg_byte.Writeback_Control 35184
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers0.throttle0.link_utilization 6.384624
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers0.throttle1.link_utilization 6.370722
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.network.routers0.throttle1.msg_count.Control::2 1470
system.ruby.network.routers0.throttle1.msg_count.Data::2 1466
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers1.throttle0.link_utilization 6.370722
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.network.routers1.throttle0.msg_count.Control::2 1470
system.ruby.network.routers1.throttle0.msg_count.Data::2 1466
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers1.throttle1.link_utilization 6.384624
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers2.throttle0.link_utilization 6.384624
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers2.throttle1.link_utilization 6.370722
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.network.routers2.throttle1.msg_count.Control::2 1470
system.ruby.network.routers2.throttle1.msg_count.Data::2 1466
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105552
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.delayVCHist.vnet_1::samples 1470 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 1470 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 1470 # delay histogram for vnet_1
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.LD.latency_hist::bucket_size 64
system.ruby.LD.latency_hist::max_bucket 639
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.LD.latency_hist::samples 1132
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.LD.latency_hist::mean 35.838339
system.ruby.LD.latency_hist::gmean 16.062923
system.ruby.LD.latency_hist::stdev 41.117345
system.ruby.LD.latency_hist | 998 88.16% 88.16% | 109 9.63% 97.79% | 13 1.15% 98.94% | 2 0.18% 99.12% | 7 0.62% 99.73% | 3 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.LD.latency_hist::total 1132
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.LD.hit_latency_hist::samples 465
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.hit_latency_hist::mean 3
system.ruby.LD.hit_latency_hist::gmean 3.000000
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist::total 465
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.LD.miss_latency_hist::bucket_size 64
system.ruby.LD.miss_latency_hist::max_bucket 639
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.LD.miss_latency_hist::samples 667
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.LD.miss_latency_hist::mean 58.731634
system.ruby.LD.miss_latency_hist::gmean 51.741753
system.ruby.LD.miss_latency_hist::stdev 39.915394
system.ruby.LD.miss_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.LD.miss_latency_hist::total 667
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.ST.latency_hist::bucket_size 32
system.ruby.ST.latency_hist::max_bucket 319
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.ST.latency_hist::samples 901
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.ST.latency_hist::mean 14.653718
system.ruby.ST.latency_hist::gmean 5.820052
system.ruby.ST.latency_hist::stdev 24.674998
system.ruby.ST.latency_hist | 684 75.92% 75.92% | 188 20.87% 96.78% | 26 2.89% 99.67% | 0 0.00% 99.67% | 0 0.00% 99.67% | 1 0.11% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.ST.latency_hist::total 901
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.ST.hit_latency_hist::samples 684
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.hit_latency_hist::mean 3
system.ruby.ST.hit_latency_hist::gmean 3.000000
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist::total 684
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.ST.miss_latency_hist::bucket_size 32
system.ruby.ST.miss_latency_hist::max_bucket 319
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.ST.miss_latency_hist::samples 217
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.ST.miss_latency_hist::mean 51.387097
system.ruby.ST.miss_latency_hist::gmean 47.001474
system.ruby.ST.miss_latency_hist::stdev 27.408897
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.ST.miss_latency_hist::total 217
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.IFETCH.latency_hist::bucket_size 32
system.ruby.IFETCH.latency_hist::max_bucket 319
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.IFETCH.latency_hist::samples 5625
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.IFETCH.latency_hist::mean 9.539378
system.ruby.IFETCH.latency_hist::gmean 4.106431
system.ruby.IFETCH.latency_hist::stdev 21.247440
system.ruby.IFETCH.latency_hist | 5039 89.58% 89.58% | 435 7.73% 97.32% | 121 2.15% 99.47% | 5 0.09% 99.56% | 8 0.14% 99.70% | 15 0.27% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.IFETCH.latency_hist::total 5625
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.IFETCH.hit_latency_hist::samples 5039
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.hit_latency_hist::mean 3
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist::total 5039
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.IFETCH.miss_latency_hist::samples 586
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.IFETCH.miss_latency_hist::mean 65.771331
system.ruby.IFETCH.miss_latency_hist::gmean 61.076979
system.ruby.IFETCH.miss_latency_hist::stdev 28.360902
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.IFETCH.miss_latency_hist::total 586
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.Directory.miss_mach_latency_hist::samples 1470
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.Directory.miss_mach_latency_hist::mean 60.453741
system.ruby.Directory.miss_mach_latency_hist::gmean 54.500138
system.ruby.Directory.miss_mach_latency_hist::stdev 34.320124
system.ruby.Directory.miss_mach_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.Directory.miss_mach_latency_hist::total 1470
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan
system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9
system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan
system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9
system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.731634
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 51.741753
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 39.915394
system.ruby.LD.Directory.miss_type_mach_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.387097
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.001474
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.408897
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.771331
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.076979
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.360902
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.Directory_Controller.GETX 1470 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00%
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 901 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1470 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 667 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 586 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 217 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 465 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 5039 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 684 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00%
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
---------- End Simulation Statistics ----------
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