2009-05-11 19:38:46 +02:00
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---------- Begin Simulation Statistics ----------
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2011-02-08 04:23:11 +01:00
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host_inst_rate 24278 # Simulator instruction rate (inst/s)
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host_mem_usage 347460 # Number of bytes of host memory used
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host_seconds 0.24 # Real time elapsed on the host
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host_tick_rate 1220626 # Simulator tick rate (ticks/s)
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2010-01-30 05:29:40 +01:00
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sim_freq 1000000000 # Frequency of simulated ticks
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2010-01-02 13:06:26 +01:00
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sim_insts 5827 # Number of instructions simulated
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2010-01-30 05:29:40 +01:00
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sim_seconds 0.000293 # Number of seconds simulated
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sim_ticks 292960 # Number of ticks simulated
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2009-05-11 19:38:46 +02:00
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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2010-01-30 05:29:40 +01:00
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system.cpu.numCycles 292960 # number of cpu cycles simulated
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2010-01-02 13:06:26 +01:00
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system.cpu.num_insts 5827 # Number of instructions executed
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2011-02-08 04:23:11 +01:00
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system.cpu.num_refs 2090 # Number of memory references
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2010-01-02 13:06:26 +01:00
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system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
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2009-05-11 19:38:46 +02:00
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---------- End Simulation Statistics ----------
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