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gem5/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt

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Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate. --HG-- extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec
2007-06-22 21:06:10 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
sim_seconds 0.387215 # Number of seconds simulated
sim_ticks 387214915500 # Number of ticks simulated
final_tick 387214915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate. --HG-- extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec
2007-06-22 21:06:10 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
host_inst_rate 118034 # Simulator instruction rate (inst/s)
host_op_rate 118406 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32618299 # Simulator tick rate (ticks/s)
host_mem_usage 226848 # Number of bytes of host memory used
host_seconds 11871.09 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytes_read::cpu.inst 78656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1678976 # Number of bytes read from this memory
system.physmem.bytes_read::total 1757632 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 78656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 78656 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 163392 # Number of bytes written to this memory
system.physmem.bytes_written::total 163392 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1229 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26234 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27463 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2553 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2553 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 203133 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4336031 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4539164 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 203133 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 203133 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 421967 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 421967 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 421967 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 203133 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4336031 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4961131 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 27464 # Total number of read requests seen
system.physmem.writeReqs 2553 # Total number of write requests seen
system.physmem.cpureqs 30017 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1757632 # Total number of bytes read from memory
system.physmem.bytesWritten 163392 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1757632 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 163392 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1703 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1746 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1716 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1734 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1804 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1768 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1668 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1679 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1758 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1623 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 172 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 165 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 161 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 387214887500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 27464 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 2553 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 6398 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 12553 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6348 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 625 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 392 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 391 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 380 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 371 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 916617704 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1530569704 # Sum of mem lat for all requests
system.physmem.totBusLat 109840000 # Total cycles spent in databus access
system.physmem.totBankLat 504112000 # Total cycles spent in bank access
system.physmem.avgQLat 33380.11 # Average queueing delay per request
system.physmem.avgBankLat 18358.05 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 55738.15 # Average memory access latency
system.physmem.avgRdBW 4.54 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 4.54 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 12.78 # Average write queue length over time
system.physmem.readRowHits 18350 # Number of row buffer hits during reads
system.physmem.writeRowHits 1423 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 55.74 # Row buffer hit rate for writes
system.physmem.avgGap 12899853.00 # Average gap between requests
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 49 # Number of system calls
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.numCycles 774429832 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.lookups 98185573 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 88408048 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3782090 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 66047653 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 65662573 # Number of BTB hits
tests: update tests because of changes in stat names and in the stats package
2009-03-07 23:30:55 +01:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.usedRAS 1362 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 165872466 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1648691883 # Number of instructions fetch has processed
system.cpu.fetch.Branches 98185573 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 65663935 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 330391084 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 21655373 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 260441698 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2775 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 162813824 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 754521 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 774378524 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.134915 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.150373 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::0 443987440 57.33% 57.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 74371964 9.60% 66.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 37979457 4.90% 71.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 9083058 1.17% 73.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 28156651 3.64% 76.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 18823006 2.43% 79.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 11516280 1.49% 80.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3872547 0.50% 81.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 146588121 18.93% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::total 774378524 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.126784 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.128911 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 216878479 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 211680769 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 285325834 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 42823062 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 17670380 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 1642440106 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 17670380 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 240852826 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 34201656 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 51873963 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 303043152 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 126736547 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1631096404 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 30920192 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 73688032 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 3125584 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1360785655 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2755532793 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2721694232 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 33838561 # Number of floating rename lookups
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.rename.UndoneMaps 116015216 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2681563 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2696177 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 272664149 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 438656145 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 180228164 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 255185830 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 83164069 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1516867754 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2636658 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1460784709 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 45870 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 113563441 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 136393501 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 392987 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 774378524 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.886396 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.429689 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::0 144522601 18.66% 18.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 185174960 23.91% 42.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 210422651 27.17% 69.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 131027562 16.92% 86.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 70858421 9.15% 95.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 20344015 2.63% 98.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7836220 1.01% 99.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 4026070 0.52% 99.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 166024 0.02% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::total 774378524 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.fu_full::IntAlu 112088 6.69% 6.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 98938 5.90% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1079860 64.44% 77.03% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 384872 22.97% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::IntAlu 867100758 59.36% 59.36% # Type of FU issued
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::FloatAdd 2647457 0.18% 59.54% # Type of FU issued
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::MemRead 419766221 28.74% 88.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 171270273 11.72% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::total 1460784709 # Type of FU issued
system.cpu.iq.rate 1.886271 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1675758 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001147 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3679920663 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1624205262 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1444366362 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 17748907 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 9099237 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 8557399 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1453373806 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 9086661 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 215387676 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 36143302 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 55137 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 245231 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 13380022 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 3602 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.iewSquashCycles 17670380 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1032740 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 13152 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1613687741 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 4121479 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 438656145 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 180228164 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2550792 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 8203 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 245231 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2357183 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1559022 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3916205 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1455236393 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 417044165 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 5548316 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.exec_nop 94183329 # number of nop insts executed
system.cpu.iew.exec_refs 587622922 # number of memory reference insts executed
system.cpu.iew.exec_branches 89108958 # Number of branches executed
system.cpu.iew.exec_stores 170578757 # Number of stores executed
system.cpu.iew.exec_rate 1.879107 # Inst execution rate
system.cpu.iew.wb_sent 1453841644 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1452923761 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1154329978 # num instructions producing a value
system.cpu.iew.wb_consumers 1205560357 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.wb_rate 1.876121 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.957505 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.commitSquashedInsts 124055997 # The number of squashed insts skipped by commit
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.branchMispredicts 3782090 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 756708755 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.968423 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.506505 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::0 238213555 31.48% 31.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 276540536 36.55% 68.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 43021375 5.69% 73.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 54822808 7.24% 80.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19645378 2.60% 83.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 13385764 1.77% 85.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 30553973 4.04% 89.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10565526 1.40% 90.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 69959840 9.25% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::total 756708755 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 1485108088 # Number of instructions committed
system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.refs 569360985 # Number of memory references committed
system.cpu.commit.loads 402512843 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 51356 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 86248928 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions.
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.bw_lim_events 69959840 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.rob.rob_reads 2300263324 # The number of ROB reads
system.cpu.rob.rob_writes 3244852707 # The number of ROB writes
system.cpu.timesIdled 1017 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51308 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 1401188945 # Number of Instructions Simulated
system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.cpi 0.552695 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.552695 # CPI: Total CPI of All Threads
system.cpu.ipc 1.809317 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.809317 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1980527314 # number of integer regfile reads
system.cpu.int_regfile_writes 1276211568 # number of integer regfile writes
system.cpu.fp_regfile_reads 16969770 # number of floating regfile reads
system.cpu.fp_regfile_writes 10498210 # number of floating regfile writes
system.cpu.misc_regfile_reads 593297660 # number of misc regfile reads
SPARC: update SE stats for FP fix --HG-- extra : rebase_source : 954a009a9f8eef6cae6050ee99f264e0fb456f85
2011-12-01 00:57:11 +01:00
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.replacements 217 # number of replacements
system.cpu.icache.tagsinuse 1045.896866 # Cycle average of tags in use
system.cpu.icache.total_refs 162811965 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1366 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 119188.846999 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.occ_blocks::cpu.inst 1045.896866 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.510692 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.510692 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 162811965 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 162811965 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 162811965 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 162811965 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 162811965 # number of overall hits
system.cpu.icache.overall_hits::total 162811965 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1859 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1859 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1859 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1859 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1859 # number of overall misses
system.cpu.icache.overall_misses::total 1859 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 53339000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 53339000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 53339000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 53339000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 53339000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 53339000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 162813824 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 162813824 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 162813824 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 162813824 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 162813824 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 162813824 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000011 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000011 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28692.307692 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28692.307692 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28692.307692 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28692.307692 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28692.307692 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28692.307692 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 492 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 492 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 492 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 492 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 492 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 492 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1367 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1367 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1367 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1367 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1367 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1367 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 40091000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 40091000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 40091000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 40091000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 40091000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 40091000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29327.724945 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29327.724945 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29327.724945 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 29327.724945 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29327.724945 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 29327.724945 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.replacements 458245 # number of replacements
system.cpu.dcache.tagsinuse 4094.164833 # Cycle average of tags in use
system.cpu.dcache.total_refs 365848378 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 462341 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 791.295555 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 304049000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.164833 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999552 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999552 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 200718396 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 200718396 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 165128663 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 165128663 # number of WriteReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_hits::cpu.data 365847059 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 365847059 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 365847059 # number of overall hits
system.cpu.dcache.overall_hits::total 365847059 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 893632 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 893632 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1718153 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1718153 # number of WriteReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_misses::cpu.data 2611785 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2611785 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2611785 # number of overall misses
system.cpu.dcache.overall_misses::total 2611785 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6936484000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6936484000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15815722499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 15815722499 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 50000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 50000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22752206499 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22752206499 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22752206499 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22752206499 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 201612028 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 201612028 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_accesses::cpu.data 368458844 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 368458844 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 368458844 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 368458844 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004432 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004432 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010298 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010298 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.007088 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.007088 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.007088 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.007088 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7762.125797 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 7762.125797 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9205.072249 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 9205.072249 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 7142.857143 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 7142.857143 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 8711.362727 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 8711.362727 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 8711.362727 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 8711.362727 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.writebacks::writebacks 443162 # number of writebacks
system.cpu.dcache.writebacks::total 443162 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 693399 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 693399 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1456052 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1456052 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2149451 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2149451 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2149451 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2149451 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200233 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 200233 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262101 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 262101 # number of WriteReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 462334 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 462334 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 462334 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 462334 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 847043500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 847043500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1875854500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1875854500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 36000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 36000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2722898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 2722898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2722898000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 2722898000 # number of overall MSHR miss cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000993 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001255 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001255 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001255 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001255 # mshr miss rate for overall accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4230.289213 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4230.289213 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7156.991007 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7156.991007 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 5142.857143 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 5142.857143 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5889.460866 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 5889.460866 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5889.460866 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 5889.460866 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.replacements 2679 # number of replacements
system.cpu.l2cache.tagsinuse 22378.512464 # Cycle average of tags in use
system.cpu.l2cache.total_refs 542084 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24310 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.298807 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.occ_blocks::writebacks 20735.512523 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 999.090351 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 643.909590 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.632798 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.030490 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019651 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.682938 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 137 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 195795 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 195932 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 443162 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 443162 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 240312 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 240312 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 137 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 436107 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 436244 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 137 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 436107 # number of overall hits
system.cpu.l2cache.overall_hits::total 436244 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1230 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4433 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5663 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21801 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21801 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1230 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 26234 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 27464 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1230 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26234 # number of overall misses
system.cpu.l2cache.overall_misses::total 27464 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38568000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 446023500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 484591500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1290023500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1290023500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 38568000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1736047000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1774615000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 38568000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1736047000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1774615000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1367 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 200228 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 201595 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 443162 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 443162 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 262113 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 262113 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1367 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 462341 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 463708 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1367 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 462341 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 463708 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.899781 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022140 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.028091 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083174 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083174 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.899781 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.056742 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.059227 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.899781 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.056742 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.059227 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31356.097561 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100614.369501 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 85571.516864 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59172.675565 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59172.675565 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31356.097561 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66175.459328 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 64616.042820 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31356.097561 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66175.459328 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 64616.042820 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 28 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate. --HG-- extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec
2007-06-22 21:06:10 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.writebacks::writebacks 2553 # number of writebacks
system.cpu.l2cache.writebacks::total 2553 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1230 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4433 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5663 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21801 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21801 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1230 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26234 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 27464 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1230 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26234 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27464 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34143480 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430451654 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 464595134 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1217504185 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1217504185 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34143480 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1647955839 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1682099319 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34143480 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1647955839 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1682099319 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022140 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028091 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083174 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083174 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056742 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.059227 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056742 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059227 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 27758.926829 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 97101.658922 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 82040.461593 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55846.254071 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55846.254071 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 27758.926829 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62817.558855 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61247.426413 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 27758.926829 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62817.558855 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61247.426413 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate. --HG-- extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec
2007-06-22 21:06:10 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink