2006-07-27 23:47:43 +02:00
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---------- Begin Simulation Statistics ----------
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2009-02-16 18:09:45 +01:00
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host_inst_rate 1953289 # Simulator instruction rate (inst/s)
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host_mem_usage 288556 # Number of bytes of host memory used
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host_seconds 28.78 # Real time elapsed on the host
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host_tick_rate 67077404616 # Simulator tick rate (ticks/s)
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2007-05-16 01:25:35 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2008-12-15 09:47:15 +01:00
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sim_insts 56205703 # Number of instructions simulated
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sim_seconds 1.930165 # Number of seconds simulated
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sim_ticks 1930164593000 # Number of ticks simulated
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system.cpu.dcache.LoadLockedReq_accesses 200404 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.546017 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_hits 183095 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.086371 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses 17309 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086371 # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.ReadReq_accesses 8888653 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 25452.354477 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.ReadReq_hits 7818479 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.120398 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1070174 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.120398 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses 199383 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.366085 # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency
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system.cpu.dcache.StoreCondReq_hits 169379 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles
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system.cpu.dcache.StoreCondReq_miss_rate 0.150484 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_misses 30004 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles
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system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150484 # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 6160337 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56004.022652 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.WriteReq_hits 5759482 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.065070 # miss rate for WriteReq accesses
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2008-08-04 00:13:29 +02:00
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system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.065070 # mshr miss rate for WriteReq accesses
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2008-08-04 00:13:29 +02:00
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system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks.
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.demand_accesses 15048990 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 33777.675695 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 13577961 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.097749 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1471029 # number of demand (read+write) misses
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2008-12-15 09:47:15 +01:00
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system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.097749 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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|
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.overall_accesses 15048990 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 33777.675695 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.overall_hits 13577961 # number of overall hits
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system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.097749 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1471029 # number of overall misses
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.097749 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.replacements 1391606 # number of replacements
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system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks.
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use
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system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks.
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2008-08-04 00:13:29 +02:00
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system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit.
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2008-12-15 09:47:15 +01:00
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system.cpu.dcache.writebacks 430459 # number of writebacks
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2008-08-04 00:13:29 +02:00
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system.cpu.dtb.accesses 1020784 # DTB accesses
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2008-02-26 08:20:40 +01:00
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system.cpu.dtb.acv 367 # DTB access violations
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2008-12-15 09:47:15 +01:00
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system.cpu.dtb.hits 15429793 # DTB hits
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2008-08-04 00:13:29 +02:00
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system.cpu.dtb.misses 11466 # DTB misses
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system.cpu.dtb.read_accesses 728853 # DTB read accesses
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2006-10-06 06:39:21 +02:00
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system.cpu.dtb.read_acv 210 # DTB read access violations
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2008-12-15 09:47:15 +01:00
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system.cpu.dtb.read_hits 9069700 # DTB read hits
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2008-08-04 00:13:29 +02:00
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system.cpu.dtb.read_misses 10324 # DTB read misses
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2008-02-26 08:20:40 +01:00
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system.cpu.dtb.write_accesses 291931 # DTB write accesses
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system.cpu.dtb.write_acv 157 # DTB write access violations
|
2008-12-15 09:47:15 +01:00
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system.cpu.dtb.write_hits 6360093 # DTB write hits
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2008-02-26 08:20:40 +01:00
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system.cpu.dtb.write_misses 1142 # DTB write misses
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2008-12-15 09:47:15 +01:00
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system.cpu.icache.ReadReq_accesses 56217537 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 14711.221983 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 55286436 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.016562 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 931101 # number of ReadReq misses
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|
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system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.016562 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses
|
2007-05-16 01:25:35 +02:00
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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2008-12-15 09:47:15 +01:00
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system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks.
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2007-05-16 01:25:35 +02:00
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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|
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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|
|
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|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2008-12-15 09:47:15 +01:00
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|
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system.cpu.icache.demand_accesses 56217537 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 14711.221983 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency
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system.cpu.icache.demand_hits 55286436 # number of demand (read+write) hits
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|
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|
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system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles
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|
|
|
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system.cpu.icache.demand_miss_rate 0.016562 # miss rate for demand accesses
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|
|
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system.cpu.icache.demand_misses 931101 # number of demand (read+write) misses
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2008-12-15 09:47:15 +01:00
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|
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system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles
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|
|
|
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system.cpu.icache.demand_mshr_miss_rate 0.016562 # mshr miss rate for demand accesses
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|
|
|
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system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
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|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.icache.overall_accesses 56217537 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 14711.221983 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.icache.overall_hits 55286436 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.016562 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 931101 # number of overall misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.016562 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.icache.replacements 930429 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 55286436 # Total number of references to valid blocks.
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.idle_fraction 0.929209 # Percentage of idle cycles
|
|
|
|
|
system.cpu.itb.accesses 4982987 # ITB accesses
|
2006-10-06 06:39:21 +02:00
|
|
|
system.cpu.itb.acv 184 # ITB acv
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.itb.hits 4977977 # ITB hits
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.itb.misses 5010 # ITB misses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.kern.callpal 193221 # number of callpals executed
|
2006-07-27 23:47:43 +02:00
|
|
|
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.kern.callpal_swpipl 176257 91.22% 93.41% # number of callpals executed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
|
2006-10-08 23:07:23 +02:00
|
|
|
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
|
2006-07-27 23:47:43 +02:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed
|
|
|
|
|
system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed
|
|
|
|
|
system.cpu.kern.ipl_count 183502 # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count_0 75001 40.87% 40.87% # number of times we switched to this ipl
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.kern.ipl_count_31 106426 58.00% 100.00% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_good 149343 # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good_0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.kern.ipl_good_31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks 1930163835000 # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks_0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks_21 96331500 0.00% 96.72% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks_22 565310500 0.03% 96.75% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks_31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_used_0 0.981774 # fraction of swpipl calls that actually changed the ipl
|
2006-07-27 23:47:43 +02:00
|
|
|
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.kern.ipl_used_31 0.691880 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu.kern.mode_good_kernel 1911
|
|
|
|
|
system.cpu.kern.mode_good_user 1744
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.mode_good_idle 167
|
|
|
|
|
system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.kern.mode_switch_user 1744 # number of protection mode switches
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.kern.mode_switch_good 1.402910 # fraction of useful protection mode switches
|
|
|
|
|
system.cpu.kern.mode_switch_good_kernel 0.322968 # fraction of useful protection mode switches
|
2006-07-27 23:47:43 +02:00
|
|
|
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.kern.mode_ticks_kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu.kern.mode_ticks_user 5539986000 0.29% 2.80% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu.kern.mode_ticks_idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.kern.swap_context 4172 # number of times the context was actually changed
|
2007-04-23 20:40:46 +02:00
|
|
|
system.cpu.kern.syscall 326 # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
|
2006-11-13 06:24:22 +01:00
|
|
|
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
|
2008-12-15 09:47:15 +01:00
|
|
|
system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.numCycles 3860329186 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.num_insts 56205703 # Number of instructions executed
|
|
|
|
|
system.cpu.num_refs 15677891 # Number of memory references
|
2006-07-27 23:47:43 +02:00
|
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
2007-04-23 20:40:46 +02:00
|
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
|
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
2006-07-27 23:47:43 +02:00
|
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
|
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
|
2008-08-04 00:13:29 +02:00
|
|
|
system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency
|
|
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency
|
|
|
|
|
system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_misses 173 # number of ReadReq misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
|
|
|
|
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.WriteReq_avg_miss_latency 137876.559636 # average WriteReq miss latency
|
|
|
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency
|
|
|
|
|
system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
|
|
|
|
|
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.avg_blocked_cycles_no_mshrs 6163.674943 # average number of cycles each access was blocked
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
2008-08-04 00:13:29 +02:00
|
|
|
system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.blocked_cycles_no_mshrs 64546004 # number of cycles access was blocked
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.demand_avg_miss_latency 137782.763427 # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.demand_hits 0 # number of demand (read+write) hits
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_misses 41725 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.overall_avg_miss_latency 137782.763427 # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.iocache.overall_hits 0 # number of overall hits
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_misses 41725 # number of overall misses
|
|
|
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.iocache.replacements 41685 # number of replacements
|
|
|
|
|
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.tagsinuse 1.353399 # Cycle average of tags in use
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
2008-12-15 09:47:15 +01:00
|
|
|
system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit.
|
2007-08-10 22:14:02 +02:00
|
|
|
system.iocache.writebacks 41512 # number of writebacks
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.ReadExReq_accesses 304636 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency 52003.289171 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.ReadExReq_misses 304636 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_accesses 2018564 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency 52016.377161 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.ReadReq_hits 1710971 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_rate 0.152382 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_misses 307593 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate 0.152382 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.UpgradeReq_accesses 126223 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency 52001.810288 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.UpgradeReq_misses 126223 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.Writeback_accesses 430459 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_hits 430459 # number of Writeback hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.avg_refs 4.436562 # Average number of references to valid blocks.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.demand_accesses 2323200 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_avg_miss_latency 52009.864773 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_hits 1710971 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_rate 0.263528 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_misses 612229 # number of demand (read+write) misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_rate 0.263528 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.overall_accesses 2323200 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_avg_miss_latency 52009.864773 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.overall_hits 1710971 # number of overall hits
|
|
|
|
|
system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_rate 0.263528 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_misses 612229 # number of overall misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_rate 0.263528 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.replacements 394928 # number of replacements
|
|
|
|
|
system.l2c.sampled_refs 425903 # Sample count of references to valid blocks.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 1889545 # Total number of references to valid blocks.
|
2008-08-04 00:13:29 +02:00
|
|
|
system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit.
|
2008-12-15 09:47:15 +01:00
|
|
|
system.l2c.writebacks 119060 # number of writebacks
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
|
2006-10-09 04:05:34 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
|
2007-01-26 01:14:05 +01:00
|
|
|
system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
|
2006-10-09 04:05:34 +02:00
|
|
|
system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
|
2007-04-23 20:40:46 +02:00
|
|
|
system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
|
2006-09-05 22:24:47 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
|
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
|
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
