2006-07-27 23:47:43 +02:00
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---------- Begin Simulation Statistics ----------
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2007-08-04 00:04:30 +02:00
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host_inst_rate 631972 # Simulator instruction rate (inst/s)
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host_mem_usage 219140 # Number of bytes of host memory used
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host_seconds 95.00 # Real time elapsed on the host
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host_tick_rate 20109299069 # Simulator tick rate (ticks/s)
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2007-05-16 01:25:35 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2007-08-04 00:04:30 +02:00
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sim_insts 60034774 # Number of instructions simulated
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sim_seconds 1.910310 # Number of seconds simulated
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sim_ticks 1910309711000 # Number of ticks simulated
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system.cpu.dcache.LoadLockedReq_accesses 200211 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 13960.656682 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12960.656682 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_hits 182851 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 242357000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.086709 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses 17360 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 224997000 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086709 # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_misses 17360 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.ReadReq_accesses 9525872 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 13240.454388 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12240.427719 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.dcache.ReadReq_hits 7801048 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 22837453500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.181067 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1724824 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 21112583500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.181067 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1724824 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 830826000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses 199189 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_avg_miss_latency 14000.798456 # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13000.798456 # average StoreCondReq mshr miss latency
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system.cpu.dcache.StoreCondReq_hits 169131 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_miss_latency 420836000 # number of StoreCondReq miss cycles
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system.cpu.dcache.StoreCondReq_miss_rate 0.150902 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_misses 30058 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_mshr_miss_latency 390778000 # number of StoreCondReq MSHR miss cycles
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system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150902 # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_misses 30058 # number of StoreCondReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 6151132 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 14000.947966 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000.947966 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_hits 5750801 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 5605013500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.065082 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 400331 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 5204682500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.065082 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 400331 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1164414500 # number of WriteReq MSHR uncacheable cycles
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.avg_refs 6.854770 # Average number of references to valid blocks.
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.demand_accesses 15677004 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 13383.714129 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 13551849 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 28442467000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.135559 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2125155 # number of demand (read+write) misses
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.demand_mshr_miss_latency 26317266000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.135559 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 2125155 # number of demand (read+write) MSHR misses
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.overall_accesses 15677004 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 13383.714129 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 13551849 # number of overall hits
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system.cpu.dcache.overall_miss_latency 28442467000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.135559 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2125155 # number of overall misses
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.overall_mshr_miss_latency 26317266000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.135559 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 2125155 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 1995240500 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.replacements 2046194 # number of replacements
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system.cpu.dcache.sampled_refs 2046706 # Sample count of references to valid blocks.
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2007-08-04 00:04:30 +02:00
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system.cpu.dcache.tagsinuse 511.987834 # Cycle average of tags in use
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system.cpu.dcache.total_refs 14029698 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 58297000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 429991 # number of writebacks
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2007-05-16 01:25:35 +02:00
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system.cpu.dtb.accesses 1020787 # DTB accesses
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2006-10-06 06:39:21 +02:00
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system.cpu.dtb.acv 367 # DTB access violations
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2007-08-04 00:04:30 +02:00
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system.cpu.dtb.hits 16056951 # DTB hits
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2007-05-16 01:25:35 +02:00
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system.cpu.dtb.misses 11471 # DTB misses
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system.cpu.dtb.read_accesses 728856 # DTB read accesses
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2006-10-06 06:39:21 +02:00
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system.cpu.dtb.read_acv 210 # DTB read access violations
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2007-08-04 00:04:30 +02:00
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system.cpu.dtb.read_hits 9706492 # DTB read hits
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2007-05-16 01:25:35 +02:00
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system.cpu.dtb.read_misses 10329 # DTB read misses
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2007-04-23 20:40:46 +02:00
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system.cpu.dtb.write_accesses 291931 # DTB write accesses
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2006-10-06 06:39:21 +02:00
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system.cpu.dtb.write_acv 157 # DTB write access violations
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2007-08-04 00:04:30 +02:00
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system.cpu.dtb.write_hits 6350459 # DTB write hits
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2007-04-23 20:40:46 +02:00
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system.cpu.dtb.write_misses 1142 # DTB write misses
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2007-08-04 00:04:30 +02:00
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system.cpu.icache.ReadReq_accesses 60034775 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 12033.060657 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.326155 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 59106935 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 11164755000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.015455 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 927840 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 10236233500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.015455 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 927840 # number of ReadReq MSHR misses
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2007-05-16 01:25:35 +02:00
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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2007-08-04 00:04:30 +02:00
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system.cpu.icache.avg_refs 63.714789 # Average number of references to valid blocks.
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2007-05-16 01:25:35 +02:00
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2007-08-04 00:04:30 +02:00
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system.cpu.icache.demand_accesses 60034775 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 12033.060657 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
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system.cpu.icache.demand_hits 59106935 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 11164755000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.015455 # miss rate for demand accesses
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system.cpu.icache.demand_misses 927840 # number of demand (read+write) misses
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2007-05-16 01:25:35 +02:00
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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2007-08-04 00:04:30 +02:00
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system.cpu.icache.demand_mshr_miss_latency 10236233500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.015455 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 927840 # number of demand (read+write) MSHR misses
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2007-05-16 01:25:35 +02:00
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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2007-08-04 00:04:30 +02:00
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system.cpu.icache.overall_accesses 60034775 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 12033.060657 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
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2007-05-16 01:25:35 +02:00
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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2007-08-04 00:04:30 +02:00
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system.cpu.icache.overall_hits 59106935 # number of overall hits
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system.cpu.icache.overall_miss_latency 11164755000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.015455 # miss rate for overall accesses
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system.cpu.icache.overall_misses 927840 # number of overall misses
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2007-05-16 01:25:35 +02:00
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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2007-08-04 00:04:30 +02:00
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system.cpu.icache.overall_mshr_miss_latency 10236233500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.015455 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 927840 # number of overall MSHR misses
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2007-05-16 01:25:35 +02:00
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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2007-08-04 00:04:30 +02:00
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system.cpu.icache.replacements 927169 # number of replacements
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system.cpu.icache.sampled_refs 927680 # Sample count of references to valid blocks.
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2007-05-16 01:25:35 +02:00
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2007-08-04 00:04:30 +02:00
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|
|
system.cpu.icache.tagsinuse 508.749374 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 59106935 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 35000367000 # Cycle when the warmup percentage was hit.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.idle_fraction 0.939637 # Percentage of idle cycles
|
|
|
|
|
system.cpu.itb.accesses 4978395 # ITB accesses
|
2006-10-06 06:39:21 +02:00
|
|
|
system.cpu.itb.acv 184 # ITB acv
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.itb.hits 4973389 # ITB hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.itb.misses 5006 # ITB misses
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.callpal 192813 # number of callpals executed
|
2006-07-27 23:47:43 +02:00
|
|
|
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.callpal_swpipl 175877 91.22% 93.42% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_rdps 6828 3.54% 96.96% # number of callpals executed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed
|
|
|
|
|
system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.callpal_rti 5152 2.67% 99.64% # number of callpals executed
|
2007-04-23 20:40:46 +02:00
|
|
|
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
|
2006-10-08 23:07:23 +02:00
|
|
|
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
|
2006-07-27 23:47:43 +02:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.inst.hwrei 211901 # number of hwrei instructions executed
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.ipl_count 183088 # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count_0 74875 40.90% 40.90% # number of times we switched to this ipl
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.ipl_count_22 1927 1.05% 42.02% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_count_31 106155 57.98% 100.00% # number of times we switched to this ipl
|
|
|
|
|
system.cpu.kern.ipl_good 149074 # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good_0 73508 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.ipl_good_22 1927 1.29% 50.69% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_good_31 73508 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks 1910308997000 # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks_0 1853401678500 97.02% 97.02% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks_21 78202500 0.00% 97.03% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks_22 538133000 0.03% 97.05% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_ticks_31 56290983000 2.95% 100.00% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu.kern.ipl_used_0 0.981743 # fraction of swpipl calls that actually changed the ipl
|
2006-07-27 23:47:43 +02:00
|
|
|
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.ipl_used_31 0.692459 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu.kern.mode_good_kernel 1908
|
|
|
|
|
system.cpu.kern.mode_good_user 1738
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.kern.mode_good_idle 170
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.mode_switch_kernel 5896 # number of protection mode switches
|
|
|
|
|
system.cpu.kern.mode_switch_user 1738 # number of protection mode switches
|
|
|
|
|
system.cpu.kern.mode_switch_idle 2098 # number of protection mode switches
|
|
|
|
|
system.cpu.kern.mode_switch_good 1.404639 # fraction of useful protection mode switches
|
|
|
|
|
system.cpu.kern.mode_switch_good_kernel 0.323609 # fraction of useful protection mode switches
|
2006-07-27 23:47:43 +02:00
|
|
|
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.kern.mode_switch_good_idle 0.081030 # fraction of useful protection mode switches
|
|
|
|
|
system.cpu.kern.mode_ticks_kernel 43115749000 2.26% 2.26% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu.kern.mode_ticks_user 4716926000 0.25% 2.50% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu.kern.mode_ticks_idle 1862476320000 97.50% 100.00% # number of ticks spent at the given mode
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
2007-04-23 20:40:46 +02:00
|
|
|
system.cpu.kern.syscall 326 # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
|
2006-11-13 06:24:22 +01:00
|
|
|
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
|
|
|
|
|
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.not_idle_fraction 0.060363 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.numCycles 1910309711000 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.num_insts 60034774 # Number of instructions executed
|
|
|
|
|
system.cpu.num_refs 16305091 # Number of memory references
|
2006-07-27 23:47:43 +02:00
|
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
2007-04-23 20:40:46 +02:00
|
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
|
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
2006-07-27 23:47:43 +02:00
|
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
|
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.ReadExReq_accesses 304522 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency 12000.719160 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 11000.719160 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_miss_latency 3654483000 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_misses 304522 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency 3349961000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses 304522 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_accesses 2670005 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency 12000.233269 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 11000.233269 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.l2c.ReadReq_hits 1568273 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_miss_latency 13221041000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_rate 0.412633 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_misses 1101732 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency 12119309000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate 0.412633 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses 1101732 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.UpgradeReq_accesses 125867 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency 11999.892744 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 11000.750793 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency 1510390500 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_misses 125867 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency 1384631500 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_misses 125867 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1051110500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.Writeback_accesses 429991 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
|
|
|
|
|
system.l2c.Writeback_misses 429991 # number of Writeback misses
|
|
|
|
|
system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
|
|
|
|
|
system.l2c.Writeback_mshr_misses 429991 # number of Writeback MSHR misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.avg_refs 1.660842 # Average number of references to valid blocks.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.demand_accesses 2974527 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_avg_miss_latency 12000.338488 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_hits 1568273 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_miss_latency 16875524000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_rate 0.472766 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_misses 1406254 # number of demand (read+write) misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.demand_mshr_miss_latency 15469270000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_rate 0.472766 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_misses 1406254 # number of demand (read+write) MSHR misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.overall_accesses 2974527 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_avg_miss_latency 12000.338488 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_hits 1568273 # number of overall hits
|
|
|
|
|
system.l2c.overall_miss_latency 16875524000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_rate 0.472766 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_misses 1406254 # number of overall misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.overall_mshr_miss_latency 15469270000 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_rate 0.472766 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_misses 1406254 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 1801212500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.replacements 947259 # number of replacements
|
|
|
|
|
system.l2c.sampled_refs 965538 # Sample count of references to valid blocks.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-04 00:04:30 +02:00
|
|
|
system.l2c.tagsinuse 15874.904757 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 1603606 # Total number of references to valid blocks.
|
|
|
|
|
system.l2c.warmup_cycle 4106790000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.l2c.writebacks 0 # number of writebacks
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
|
2006-10-09 04:05:34 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
|
2007-01-26 01:14:05 +01:00
|
|
|
system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
|
2006-10-09 04:05:34 +02:00
|
|
|
system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
|
2007-04-23 20:40:46 +02:00
|
|
|
system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
|
2006-09-05 22:24:47 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
|
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
|
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
