2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2016-02-24 10:16:59 +01:00
sim_seconds 51.759374 # Number of seconds simulated
sim_ticks 51759374264500 # Number of ticks simulated
final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-05-31 12:07:18 +02:00
host_inst_rate 790659 # Simulator instruction rate (inst/s)
host_op_rate 929140 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 48897567060 # Simulator tick rate (ticks/s)
host_mem_usage 670860 # Number of bytes of host memory used
host_seconds 1058.53 # Real time elapsed on the host
2016-02-24 10:16:59 +01:00
sim_insts 836933434 # Number of instructions simulated
sim_ops 983519389 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-02-24 10:16:59 +01:00
system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory
system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 63133056 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
2016-02-24 10:16:59 +01:00
system.physmem.bytes_written::total 63153636 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 2426 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2490 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 114528 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 567741 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6242 # Number of read requests responded to by this memory
system.physmem.num_reads::total 693427 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 986454 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
2016-02-24 10:16:59 +01:00
system.physmem.num_writes::total 989027 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 3000 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 3079 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 91650 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 701991 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 7718 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 807437 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 91650 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 91650 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1219741 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1220139 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1219741 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 3000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 91650 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 702388 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 7718 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2027576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 693427 # Number of read requests accepted
system.physmem.writeReqs 989027 # Number of write requests accepted
system.physmem.readBursts 693427 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 989027 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 44328448 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 50880 # Total number of bytes read from write queue
system.physmem.bytesWritten 63152448 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 41792444 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 63153636 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 795 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-02-24 10:16:59 +01:00
system.physmem.perBankRdBursts::0 40853 # Per bank write bursts
system.physmem.perBankRdBursts::1 42497 # Per bank write bursts
system.physmem.perBankRdBursts::2 39380 # Per bank write bursts
system.physmem.perBankRdBursts::3 40815 # Per bank write bursts
system.physmem.perBankRdBursts::4 36874 # Per bank write bursts
system.physmem.perBankRdBursts::5 45606 # Per bank write bursts
system.physmem.perBankRdBursts::6 38207 # Per bank write bursts
system.physmem.perBankRdBursts::7 36804 # Per bank write bursts
system.physmem.perBankRdBursts::8 38817 # Per bank write bursts
system.physmem.perBankRdBursts::9 83381 # Per bank write bursts
system.physmem.perBankRdBursts::10 47849 # Per bank write bursts
system.physmem.perBankRdBursts::11 45678 # Per bank write bursts
system.physmem.perBankRdBursts::12 39735 # Per bank write bursts
system.physmem.perBankRdBursts::13 40223 # Per bank write bursts
system.physmem.perBankRdBursts::14 37028 # Per bank write bursts
system.physmem.perBankRdBursts::15 38885 # Per bank write bursts
system.physmem.perBankWrBursts::0 61132 # Per bank write bursts
system.physmem.perBankWrBursts::1 62574 # Per bank write bursts
system.physmem.perBankWrBursts::2 60681 # Per bank write bursts
system.physmem.perBankWrBursts::3 62576 # Per bank write bursts
system.physmem.perBankWrBursts::4 57559 # Per bank write bursts
system.physmem.perBankWrBursts::5 64093 # Per bank write bursts
system.physmem.perBankWrBursts::6 59756 # Per bank write bursts
system.physmem.perBankWrBursts::7 59796 # Per bank write bursts
system.physmem.perBankWrBursts::8 61252 # Per bank write bursts
system.physmem.perBankWrBursts::9 63246 # Per bank write bursts
system.physmem.perBankWrBursts::10 66784 # Per bank write bursts
system.physmem.perBankWrBursts::11 64593 # Per bank write bursts
system.physmem.perBankWrBursts::12 60371 # Per bank write bursts
system.physmem.perBankWrBursts::13 61779 # Per bank write bursts
system.physmem.perBankWrBursts::14 59591 # Per bank write bursts
system.physmem.perBankWrBursts::15 60974 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-02-24 10:16:59 +01:00
system.physmem.numWrRetry 25 # Number of times write queue was full causing retry
system.physmem.totGap 51759371327500 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43101 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-02-24 10:16:59 +01:00
system.physmem.readPktSize::6 650311 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-02-24 10:16:59 +01:00
system.physmem.writePktSize::6 986454 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 663933 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 23086 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 455 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 539 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 542 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 655 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 269 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 154 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see
2016-02-24 10:16:59 +01:00
system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-02-24 10:16:59 +01:00
system.physmem.wrQLenPdf::15 32057 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 37802 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 55171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 54666 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 57679 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 55454 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 58825 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 55973 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 56654 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 56029 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 57159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 59457 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 57206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 57286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 59007 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 55988 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 54822 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 54598 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 2305 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 699 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 443 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 278 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 441826 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 243.264489 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 146.730249 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 285.608942 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 196692 44.52% 44.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 117501 26.59% 71.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 39119 8.85% 79.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 20402 4.62% 84.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 13280 3.01% 87.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 8813 1.99% 89.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7349 1.66% 91.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5826 1.32% 92.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 32844 7.43% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 441826 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 52334 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 13.234628 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 140.708770 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 52332 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 52334 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 52334 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.854989 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.140951 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 8.267205 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 48626 92.91% 92.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 1874 3.58% 96.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 113 0.22% 96.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 103 0.20% 96.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 52 0.10% 97.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 95 0.18% 97.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 242 0.46% 97.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 26 0.05% 97.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 308 0.59% 98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 80 0.15% 98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 37 0.07% 98.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 50 0.10% 98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 303 0.58% 99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 32 0.06% 99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 32 0.06% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 137 0.26% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 171 0.33% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads
2016-02-10 10:08:27 +01:00
system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads
2016-02-24 10:16:59 +01:00
system.physmem.wrPerTurnAround::104-107 3 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 10 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads
2016-02-10 10:08:27 +01:00
system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
2016-02-24 10:16:59 +01:00
system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 52334 # Writes before turning the bus around for reads
system.physmem.totQLat 9243736951 # Total ticks spent queuing
system.physmem.totMemAccLat 22230586951 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 3463160000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13345.81 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-02-24 10:16:59 +01:00
system.physmem.avgMemAccLat 32095.81 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.86 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.81 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
2014-10-30 05:50:15 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2014-10-30 05:50:15 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2016-02-24 10:16:59 +01:00
system.physmem.avgWrQLen 26.31 # Average write queue length when enqueuing
system.physmem.readRowHits 510166 # Number of row buffer hits during reads
system.physmem.writeRowHits 727396 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.66 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.71 # Row buffer hit rate for writes
system.physmem.avgGap 30764211.88 # Average gap between requests
system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1653765120 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 902352000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2504080800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3163322160 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1281472530255 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29931523073250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34601889523185 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.514508 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49793449587940 # Time in different power states
system.physmem_0.memoryStateTime::REF 1728359100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-24 10:16:59 +01:00
system.physmem_0.memoryStateTime::ACT 237560965810 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-02-24 10:16:59 +01:00
system.physmem_1.actEnergy 1686439440 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 920180250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2898409800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3230863200 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1285016955840 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.532817 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states
system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-24 10:16:59 +01:00
system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu.dtb.walker.walks 187211 # Table walker walks requested
system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-2047 187192 100.00% 100.00% # Table walker wait (enqueue to first request) latency
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2015-09-25 13:27:03 +02:00
system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-02-24 10:16:59 +01:00
system.cpu.dtb.walker.walkWaitTime::total 187194 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 158446 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 24872.701110 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 20850.948689 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 18486.762457 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 157188 99.21% 99.21% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.21% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 1079 0.68% 99.89% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 28 0.02% 99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 21 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 47 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 158446 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples -5153633892 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 1.304072 # Table walker pending requests distribution
2016-02-10 10:08:27 +01:00
system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
2016-02-24 10:16:59 +01:00
system.cpu.dtb.walker.walksPending::0 1567075704 -30.41% -30.41% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::1 -6720709596 130.41% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total -5153633892 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 146093 92.21% 92.21% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 12337 7.79% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 158430 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 187211 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 187211 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 158430 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 158430 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 345641 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2016-02-24 10:16:59 +01:00
system.cpu.dtb.read_hits 157500215 # DTB read hits
system.cpu.dtb.read_misses 138721 # DTB read misses
system.cpu.dtb.write_hits 142992331 # DTB write hits
system.cpu.dtb.write_misses 48490 # DTB write misses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 71001 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-02-24 10:16:59 +01:00
system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-24 10:16:59 +01:00
system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 157638936 # DTB read accesses
system.cpu.dtb.write_accesses 143040821 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2016-02-24 10:16:59 +01:00
system.cpu.dtb.hits 300492546 # DTB hits
system.cpu.dtb.misses 187211 # DTB misses
system.cpu.dtb.accesses 300679757 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu.itb.walker.walks 119486 # Table walker walks requested
system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28670.651516 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24724.680347 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 21871.977834 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 107545 98.63% 98.63% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 98.63% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 1290 1.18% 99.82% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 34 0.03% 99.85% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 71 0.07% 99.91% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 41 0.04% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 42 0.04% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 109038 # Table walker service (enqueue to completion) latency
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution
2016-02-24 10:16:59 +01:00
system.cpu.itb.walker.walkPageSizes::4K 107916 98.97% 98.97% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 109038 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119486 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 119486 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109038 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 109038 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 228524 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 837449249 # ITB inst hits
system.cpu.itb.inst_misses 119486 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 50677 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2016-02-24 10:16:59 +01:00
system.cpu.itb.inst_accesses 837568735 # ITB inst accesses
system.cpu.itb.hits 837449249 # DTB hits
system.cpu.itb.misses 119486 # DTB misses
system.cpu.itb.accesses 837568735 # DTB accesses
system.cpu.numCycles 103518748529 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-10-10 23:45:41 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2016-02-24 10:16:59 +01:00
system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed
system.cpu.committedInsts 836933434 # Number of instructions committed
system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 901230 # Number of float alu accesses
system.cpu.num_func_calls 50188688 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 127012937 # number of instructions that are conditional controls
system.cpu.num_int_insts 904020212 # number of integer instructions
system.cpu.num_fp_insts 901230 # number of float instructions
system.cpu.num_int_register_reads 1309570840 # number of times the integer registers were read
system.cpu.num_int_register_writes 716549182 # number of times the integer registers were written
system.cpu.num_fp_register_reads 1454726 # number of times the floating registers were read
system.cpu.num_fp_register_writes 760848 # number of times the floating registers were written
system.cpu.num_cc_register_reads 217149735 # number of times the CC registers were read
system.cpu.num_cc_register_writes 216544825 # number of times the CC registers were written
system.cpu.num_mem_refs 300471292 # number of memory refs
system.cpu.num_load_insts 157490392 # Number of load instructions
system.cpu.num_store_insts 142980900 # Number of store instructions
system.cpu.num_idle_cycles 100455078038.626068 # Number of idle cycles
system.cpu.num_busy_cycles 3063670490.373941 # Number of busy cycles
system.cpu.not_idle_fraction 0.029595 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.970405 # Percentage of idle cycles
system.cpu.Branches 186768786 # Number of branches fetched
2014-10-30 05:50:15 +01:00
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
2016-02-24 10:16:59 +01:00
system.cpu.op_class::IntAlu 681265861 69.23% 69.23% # Class of executed instruction
system.cpu.op_class::IntMult 2131844 0.22% 69.45% # Class of executed instruction
system.cpu.op_class::IntDiv 96991 0.01% 69.46% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction
system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction
system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction
2014-10-30 05:50:15 +01:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-02-24 10:16:59 +01:00
system.cpu.op_class::total 984078328 # Class of executed instruction
system.cpu.dcache.tags.replacements 9381962 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit.
2016-02-24 10:16:59 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-24 10:16:59 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-02-24 10:16:59 +01:00
system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_hits::cpu.data 283534216 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 283534216 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 283908330 # number of overall hits
system.cpu.dcache.overall_hits::total 283908330 # number of overall hits
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1998130 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1136451 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1136451 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1221510 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1221510 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_misses::cpu.data 8114631 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 8114631 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9251082 # number of overall misses
system.cpu.dcache.overall_misses::total 9251082 # number of overall misses
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 70206054500 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48228758000 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 48228758000 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 202906742000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 202906742000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 202906742000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 202906742000 # number of overall miss cycles
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 137764276 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1510565 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1510565 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1554131 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1554131 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3623892 # number of StoreCondReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_accesses::cpu.data 291648847 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 291648847 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 293159412 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 293159412 # number of overall (read+write) accesses
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032134 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.032134 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014504 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.014504 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752335 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.752335 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785976 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.785976 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.027823 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.027823 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.031556 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.031556 # miss rate for overall accesses
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35135.879297 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39482.900672 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39482.900672 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25005.048535 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21933.298397 # average overall miss latency
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-02-24 10:16:59 +01:00
system.cpu.dcache.writebacks::writebacks 7313678 # number of writebacks
system.cpu.dcache.writebacks::total 7313678 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21254 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 21254 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68600 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 68600 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 43235 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 43235 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 43235 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 43235 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4873010 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 4873010 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1976876 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1976876 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1134686 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1134686 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221510 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1221510 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 218778 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 218778 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 8071396 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 8071396 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9206082 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9206082 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78281972500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 78281972500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67251605000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 67251605000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21441642000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21441642000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 47007248000 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 47007248000 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 192540825500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 213982467500 # number of overall MSHR miss cycles
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles
2016-04-21 10:48:24 +02:00
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199681500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199681500 # number of overall MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014350 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751167 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751167 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785976 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785976 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027675 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.027675 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031403 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031403 # mshr miss rate for overall accesses
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34019.131701 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18896.542303 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18896.542303 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38482.900672 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38482.900672 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
2016-04-21 10:48:24 +02:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency
2016-04-21 10:48:24 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.cpu.icache.tags.replacements 13331164 # number of replacements
system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-24 10:16:59 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-02-24 10:16:59 +01:00
system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses
system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 824117568 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 824117568 # number of overall hits
system.cpu.icache.overall_hits::total 824117568 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 13331681 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 13331681 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 13331681 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 13331681 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 13331681 # number of overall misses
system.cpu.icache.overall_misses::total 13331681 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 182292722500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 182292722500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 182292722500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 182292722500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 182292722500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 182292722500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 837449249 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 837449249 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 837449249 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 837449249 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 837449249 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 837449249 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015919 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.015919 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.015919 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.015919 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.015919 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.015919 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13673.648694 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13673.648694 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13673.648694 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13673.648694 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-02-24 10:16:59 +01:00
system.cpu.icache.writebacks::writebacks 13331164 # number of writebacks
system.cpu.icache.writebacks::total 13331164 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13331681 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 13331681 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 13331681 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 13331681 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 13331681 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 13331681 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168961041500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 168961041500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168961041500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 168961041500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168961041500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 168961041500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015919 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.015919 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.015919 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12673.648694 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12673.648694 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.tags.replacements 1036266 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1098550 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 37.921538 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 38127.362532 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 231.236011 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 356.535935 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7851.500133 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 18688.418163 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.581777 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003528 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005440 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119804 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.285163 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.995713 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62027 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2434 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5507 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53647 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 372058779 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 372058779 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 313678 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242392 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 556070 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 7313678 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 7313678 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 13329610 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 13329610 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 9057 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 9057 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1592946 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1592946 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13260241 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 13260241 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5999138 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 5999138 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 739812 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 739812 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 313678 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 242392 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 13260241 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7592084 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 21408395 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 313678 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 242392 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 13260241 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7592084 # number of overall hits
system.cpu.l2cache.overall_hits::total 21408395 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2426 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2490 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4916 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 33285 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 33285 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 341588 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 341588 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 71440 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 71440 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 227336 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 227336 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 481698 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 481698 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2426 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2490 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 71440 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 568924 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 645280 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2426 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2490 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 71440 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 568924 # number of overall misses
system.cpu.l2cache.overall_misses::total 645280 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 332065500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345888500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 677954000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1332961000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1332961000 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 44822292500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 44822292500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9464687500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 9464687500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30322723500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 30322723500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 542500 # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 332065500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345888500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 9464687500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 75145016000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 85287657500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 332065500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345888500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 9464687500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 75145016000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 85287657500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 316104 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244882 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 560986 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 7313678 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 7313678 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 13329610 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 13329610 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 42342 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 42342 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1934534 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1934534 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13331681 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 13331681 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6226474 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 6226474 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1221510 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total 1221510 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 316104 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 244882 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 13331681 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 8161008 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 22053675 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 316104 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 244882 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 13331681 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 8161008 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 22053675 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007675 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010168 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.786099 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.786099 # miss rate for UpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.176574 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.176574 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005359 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005359 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036511 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036511 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.394346 # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.394346 # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007675 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010168 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005359 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.069712 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.029260 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007675 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010168 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005359 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.069712 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.029260 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136877.782358 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138911.044177 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137907.648495 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40046.898002 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40046.898002 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131217.409569 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131217.409569 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132484.427492 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132484.427492 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133382.849615 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133382.849615 # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 1.126224 # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 1.126224 # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 132171.549560 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 132171.549560 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.writebacks::writebacks 879823 # number of writebacks
system.cpu.l2cache.writebacks::total 879823 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2426 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2490 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4916 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33285 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 33285 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341588 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 341588 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 71440 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 71440 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 227336 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 227336 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 481698 # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total 481698 # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2426 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2490 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 71440 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 568924 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 645280 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2426 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2490 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 71440 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 568924 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 645280 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 307805500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 320988500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 628794000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2261111000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2261111000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41406412500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41406412500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8750287500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8750287500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28049107014 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28049107014 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 32589969500 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 32589969500 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 307805500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 320988500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8750287500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69455519514 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 78834601014 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 307805500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 320988500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8750287500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69455519514 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 78834601014 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777601500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675326000 # number of ReadReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777601500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675326000 # number of overall MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786099 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786099 # mshr miss rate for UpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176574 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176574 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005359 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036511 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394346 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394346 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.029260 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.029260 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127907.648495 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67931.831155 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67931.831155 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121217.409569 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121217.409569 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122484.427492 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122484.427492 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123381.721390 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123381.721390 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67656.435152 # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67656.435152 # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency
2016-04-21 10:48:24 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 42346 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1934534 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1934534 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 13331681 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 6235371 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1328174 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1221510 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40080776 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28367342 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601942 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 864211 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 69914271 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1706594580 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 990623790 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2528832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2701706258 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1612380 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 25039605 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.019510 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.138308 # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.snoop_fanout::0 24551092 98.05% 98.05% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 488513 1.95% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.snoop_fanout::total 25039605 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 43904381000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 1555895 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.trans_dist::ReadReq 40345 # Transaction distribution
system.iobus.trans_dist::ReadResp 40345 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231048 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231048 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334624 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size::total 7492544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer23.occupancy 25723500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iocache.tags.replacements 115506 # number of replacements
system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2016-02-24 10:16:59 +01:00
system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks.
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2016-02-24 10:16:59 +01:00
system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-02-24 10:16:59 +01:00
system.iocache.tags.tag_accesses 1040073 # Number of tag accesses
system.iocache.tags.data_accesses 1040073 # Number of data accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_misses::realview.ide 115524 # number of demand (read+write) misses
system.iocache.demand_misses::total 115564 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2016-04-21 10:48:24 +02:00
system.iocache.overall_misses::realview.ide 115524 # number of overall misses
system.iocache.overall_misses::total 115564 # number of overall misses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles
2016-04-21 10:48:24 +02:00
system.iocache.demand_miss_latency::realview.ide 15039886864 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 15045307864 # number of demand (read+write) miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles
2016-04-21 10:48:24 +02:00
system.iocache.overall_miss_latency::realview.ide 15039886864 # number of overall miss cycles
system.iocache.overall_miss_latency::total 15045307864 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2016-04-21 10:48:24 +02:00
system.iocache.demand_accesses::realview.ide 115524 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115564 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2016-04-21 10:48:24 +02:00
system.iocache.overall_accesses::realview.ide 115524 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115564 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 183847.869752 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 183653.155670 # average ReadReq miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
2016-04-21 10:48:24 +02:00
system.iocache.demand_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 130190.265688 # average overall miss latency
2016-02-24 10:16:59 +01:00
system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
2016-04-21 10:48:24 +02:00
system.iocache.overall_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 130190.265688 # average overall miss latency
2016-02-24 10:16:59 +01:00
system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-02-24 10:16:59 +01:00
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 8860 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8897 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_mshr_misses::realview.ide 115524 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115564 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2016-04-21 10:48:24 +02:00
system.iocache.overall_mshr_misses::realview.ide 115524 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115564 # number of overall MSHR misses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles
2016-04-21 10:48:24 +02:00
system.iocache.demand_mshr_miss_latency::realview.ide 9258497007 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9261918007 # number of demand (read+write) MSHR miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles
2016-04-21 10:48:24 +02:00
system.iocache.overall_mshr_miss_latency::realview.ide 9258497007 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9261918007 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133847.869752 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 133653.155670 # average ReadReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
2016-04-21 10:48:24 +02:00
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
2016-02-24 10:16:59 +01:00
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
2016-04-21 10:48:24 +02:00
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 76827 # Transaction distribution
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::ReadResp 389416 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 33708 # Transaction distribution
system.membus.trans_dist::WriteResp 33708 # Transaction distribution
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution
system.membus.trans_dist::CleanEvict 164302 # Transaction distribution
system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
system.membus.trans_dist::ReadExReq 341030 # Transaction distribution
system.membus.trans_dist::ReadExResp 341030 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 312589 # Transaction distribution
system.membus.trans_dist::InvalidateReq 588355 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2930961 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3060653 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237312 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237312 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3297965 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97722208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97892034 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7223872 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7223872 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 105115906 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3315 # Total snoops (count)
system.membus.snoop_fanout::samples 2537144 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::1 2537144 100.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::total 2537144 # Request fanout histogram
system.membus.reqLayer0.occupancy 106903500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
