2014-05-10 00:58:48 +02:00
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# Copyright (c) 2012-2014 ARM Limited
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2012-09-21 17:48:13 +02:00
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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2013-08-19 09:52:30 +02:00
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# Copyright (c) 2013 Amin Farmahini-Farahani
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# All rights reserved.
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#
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2012-09-21 17:48:13 +02:00
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Hansson
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# Ani Udipi
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from m5.params import *
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from AbstractMemory import *
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# Enum for memory scheduling algorithms, currently First-Come
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# First-Served and a First-Row Hit then First-Come First-Served
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class MemSched(Enum): vals = ['fcfs', 'frfcfs']
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2014-03-23 16:11:53 +01:00
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# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
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# channel, rank, bank, row and column, respectively, and going from
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# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
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# suitable for an open-page policy, optimising for sequential accesses
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# hitting in the open row. For a closed-page policy, RoCoRaBaCh
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# maximises parallelism.
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class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
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2012-09-21 17:48:13 +02:00
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2014-03-23 16:12:08 +01:00
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# Enum for the page policy, either open, open_adaptive, close, or
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# close_adaptive.
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class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
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'close_adaptive']
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2012-09-21 17:48:13 +02:00
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2014-03-23 16:12:12 +01:00
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# DRAMCtrl is a single-channel single-ported DRAM controller model
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2012-09-21 17:48:13 +02:00
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# that aims to model the most important system-level performance
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# effects of a DRAM without getting into too much detail of the DRAM
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# itself.
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2014-03-23 16:12:12 +01:00
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class DRAMCtrl(AbstractMemory):
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type = 'DRAMCtrl'
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cxx_header = "mem/dram_ctrl.hh"
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2012-09-21 17:48:13 +02:00
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# single-ported on the system interface side, instantiate with a
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# bus in front of the controller for multiple ports
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port = SlavePort("Slave port")
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2014-11-14 09:53:48 +01:00
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# the basic configuration of the controller architecture, note
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# that each entry corresponds to a burst for the specific DRAM
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# configuration (e.g. x32 with burst length 8 is 32 bytes) and not
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# the cacheline size or request/packet size
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2014-03-23 16:12:10 +01:00
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write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
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2013-11-01 16:56:25 +01:00
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read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
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2012-09-21 17:48:13 +02:00
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2014-03-23 16:12:01 +01:00
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# threshold in percent for when to forcefully trigger writes and
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# start emptying the write buffer
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write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
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2013-11-01 16:56:25 +01:00
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2014-03-23 16:12:01 +01:00
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# threshold in percentage for when to start writes if the read
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# queue is empty
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write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
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# minimum write bursts to schedule before switching back to reads
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min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
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"switching to reads")
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2012-09-21 17:48:13 +02:00
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# scheduler, address map and page policy
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2013-01-31 13:49:14 +01:00
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mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
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2015-02-03 20:25:52 +01:00
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addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
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2014-03-23 16:12:10 +01:00
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page_policy = Param.PageManage('open_adaptive', "Page management policy")
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2012-09-21 17:48:13 +02:00
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2014-03-23 16:12:03 +01:00
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# enforce a limit on the number of accesses per row
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max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
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"closing");
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2014-10-21 00:03:52 +02:00
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# size of DRAM Chip in Bytes
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device_size = Param.MemorySize("Size of DRAM chip")
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2013-05-30 18:54:12 +02:00
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# pipeline latency of the controller and PHY, split into a
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# frontend part and a backend part, with reads and writes serviced
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# by the queues only seeing the frontend contribution, and reads
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# serviced by the memory seeing the sum of the two
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static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
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static_backend_latency = Param.Latency("10ns", "Static backend latency")
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2013-01-31 13:49:14 +01:00
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# the physical organisation of the DRAM
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2013-08-19 09:52:30 +02:00
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device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
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"device/chip")
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burst_length = Param.Unsigned("Burst lenght (BL) in beats")
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device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
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"device/chip")
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devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
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2013-01-31 13:49:14 +01:00
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ranks_per_channel = Param.Unsigned("Number of ranks per channel")
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2014-09-20 23:18:21 +02:00
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# default to 0 bank groups per rank, indicating bank group architecture
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# is not used
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# update per memory class when bank group architecture is supported
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bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
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2013-01-31 13:49:14 +01:00
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banks_per_rank = Param.Unsigned("Number of banks per rank")
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2013-03-01 19:20:22 +01:00
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# only used for the address mapping as the controller by
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# construction is a single channel and multiple controllers have
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# to be instantiated for a multi-channel configuration
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channels = Param.Unsigned(1, "Number of channels")
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2013-01-31 13:49:14 +01:00
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2014-07-25 11:05:59 +02:00
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# For power modelling we need to know if the DRAM has a DLL or not
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dll = Param.Bool(True, "DRAM has DLL or not")
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# DRAMPower provides in addition to the core power, the possibility to
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# include RD/WR termination and IO power. This calculation assumes some
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# default values. The integration of DRAMPower with gem5 does not include
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# IO and RD/WR termination power by default. This might be added as an
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# additional feature in the future.
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2012-09-21 17:48:13 +02:00
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# timing behaviour and constraints - all in nanoseconds
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2014-05-10 00:58:49 +02:00
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# the base clock period of the DRAM
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tCK = Param.Latency("Clock period")
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2012-09-21 17:48:13 +02:00
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# the amount of time in nanoseconds from issuing an activate command
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# to the data being available in the row buffer for a read/write
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2013-01-31 13:49:14 +01:00
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tRCD = Param.Latency("RAS to CAS delay")
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2012-09-21 17:48:13 +02:00
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# the time from issuing a read/write command to seeing the actual data
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2013-01-31 13:49:14 +01:00
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tCL = Param.Latency("CAS latency")
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2012-09-21 17:48:13 +02:00
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# minimum time between a precharge and subsequent activate
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2013-01-31 13:49:14 +01:00
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tRP = Param.Latency("Row precharge time")
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2012-09-21 17:48:13 +02:00
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2013-11-01 16:56:16 +01:00
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# minimum time between an activate and a precharge to the same row
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tRAS = Param.Latency("ACT to PRE delay")
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2014-05-10 00:58:48 +02:00
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# minimum time between a write data transfer and a precharge
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tWR = Param.Latency("Write recovery time")
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2014-05-10 00:58:48 +02:00
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# minimum time between a read and precharge command
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tRTP = Param.Latency("Read to precharge")
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2012-09-21 17:48:13 +02:00
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# time to complete a burst transfer, typically the burst length
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# divided by two due to the DDR bus, but by making it a parameter
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# it is easier to also evaluate SDR memories like WideIO.
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2013-08-19 09:52:30 +02:00
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# This parameter has to account for burst length.
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# Read/Write requests with data size larger than one full burst are broken
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2014-03-23 16:12:12 +01:00
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# down into multiple requests in the controller
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2014-09-20 23:18:21 +02:00
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# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
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# With bank group architectures, tBURST represents the CAS-to-CAS
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# delay for bursts to different bank groups (tCCD_S)
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2013-01-31 13:49:14 +01:00
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tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
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2012-09-21 17:48:13 +02:00
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2014-09-20 23:18:21 +02:00
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# CAS-to-CAS delay for bursts to the same bank group
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# only utilized with bank group architectures; set to 0 for default case
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# tBURST is equivalent to tCCD_S; no explicit parameter required
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# for CAS-to-CAS delay for bursts to different bank groups
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tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
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2012-09-21 17:48:13 +02:00
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# time taken to complete one refresh cycle (N rows in all banks)
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2013-01-31 13:49:14 +01:00
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tRFC = Param.Latency("Refresh cycle time")
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2012-09-21 17:48:13 +02:00
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# refresh command interval, how often a "ref" command needs
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# to be sent. It is 7.8 us for a 64ms refresh requirement
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2013-01-31 13:49:14 +01:00
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tREFI = Param.Latency("Refresh command interval")
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2012-09-21 17:48:13 +02:00
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2014-09-20 23:17:57 +02:00
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# write-to-read, same rank turnaround penalty
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tWTR = Param.Latency("Write to read, same rank switching time")
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2012-09-21 17:48:13 +02:00
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2014-09-20 23:17:57 +02:00
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# read-to-write, same rank turnaround penalty
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tRTW = Param.Latency("Read to write, same rank switching time")
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# rank-to-rank bus delay penalty
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# this does not correlate to a memory timing parameter and encompasses:
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# 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
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# different rank bus delay
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tCS = Param.Latency("Rank to rank switching time")
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2014-05-10 00:58:48 +02:00
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2013-11-01 16:56:24 +01:00
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# minimum row activate to row activate delay time
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tRRD = Param.Latency("ACT to ACT delay")
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2014-09-20 23:18:21 +02:00
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# only utilized with bank group architectures; set to 0 for default case
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tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
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2013-01-31 13:49:14 +01:00
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# time window in which a maximum number of activates are allowed
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# to take place, set to 0 to disable
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2013-01-31 13:49:14 +01:00
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tXAW = Param.Latency("X activation window")
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activation_limit = Param.Unsigned("Max number of activates in window")
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2013-01-31 13:49:14 +01:00
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2014-07-25 11:05:59 +02:00
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# time to exit power-down mode
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# Exit power-down to next valid command delay
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tXP = Param.Latency("0ns", "Power-up Delay")
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# Exit Powerdown to commands requiring a locked DLL
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tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
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# time to exit self-refresh mode
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tXS = Param.Latency("0ns", "Self-refresh exit latency")
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# time to exit self-refresh mode with locked DLL
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tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
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2013-01-31 13:49:14 +01:00
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# Currently rolled into other params
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2012-09-21 17:48:13 +02:00
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######################################################################
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2013-11-01 16:56:16 +01:00
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# tRC - assumed to be tRAS + tRP
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2012-09-21 17:48:13 +02:00
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2014-07-25 11:05:59 +02:00
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# Power Behaviour and Constraints
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# DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
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# defined as VDD and VDD2. Each current is defined for each voltage domain
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# separately. For example, current IDD0 is active-precharge current for
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# voltage domain VDD and current IDD02 is active-precharge current for
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# voltage domain VDD2.
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# By default all currents are set to 0mA. Users who are only interested in
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# the performance of DRAMs can leave them at 0.
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# Operating 1 Bank Active-Precharge current
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IDD0 = Param.Current("0mA", "Active precharge current")
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# Operating 1 Bank Active-Precharge current multiple voltage Range
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IDD02 = Param.Current("0mA", "Active precharge current VDD2")
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# Precharge Power-down Current: Slow exit
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IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
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# Precharge Power-down Current: Slow exit multiple voltage Range
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IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
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# Precharge Power-down Current: Fast exit
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IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
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# Precharge Power-down Current: Fast exit multiple voltage Range
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IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
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# Precharge Standby current
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IDD2N = Param.Current("0mA", "Precharge Standby current")
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# Precharge Standby current multiple voltage range
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IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
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# Active Power-down current: slow exit
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IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
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# Active Power-down current: slow exit multiple voltage range
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IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
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# Active Power-down current : fast exit
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IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
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# Active Power-down current : fast exit multiple voltage range
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IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
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# Active Standby current
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IDD3N = Param.Current("0mA", "Active Standby current")
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# Active Standby current multiple voltage range
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IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
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# Burst Read Operating Current
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IDD4R = Param.Current("0mA", "READ current")
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# Burst Read Operating Current multiple voltage range
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IDD4R2 = Param.Current("0mA", "READ current VDD2")
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# Burst Write Operating Current
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IDD4W = Param.Current("0mA", "WRITE current")
|
|
|
|
|
|
|
|
# Burst Write Operating Current multiple voltage range
|
|
|
|
IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
|
|
|
|
|
|
|
|
# Refresh Current
|
|
|
|
IDD5 = Param.Current("0mA", "Refresh current")
|
|
|
|
|
|
|
|
# Refresh Current multiple voltage range
|
|
|
|
IDD52 = Param.Current("0mA", "Refresh current VDD2")
|
|
|
|
|
|
|
|
# Self-Refresh Current
|
|
|
|
IDD6 = Param.Current("0mA", "Self-refresh Current")
|
|
|
|
|
|
|
|
# Self-Refresh Current multiple voltage range
|
|
|
|
IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
|
|
|
|
|
|
|
|
# Main voltage range of the DRAM
|
|
|
|
VDD = Param.Voltage("0V", "Main Voltage Range")
|
|
|
|
|
|
|
|
# Second voltage range defined by some DRAMs
|
|
|
|
VDD2 = Param.Voltage("0V", "2nd Voltage Range")
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# A single DDR3-1600 x64 channel (one command and address bus), with
|
|
|
|
# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
|
2014-07-25 11:05:59 +02:00
|
|
|
# an 8x8 configuration.
|
2014-03-23 16:12:12 +01:00
|
|
|
class DDR3_1600_x64(DRAMCtrl):
|
2014-10-21 00:03:52 +02:00
|
|
|
# size of device in bytes
|
|
|
|
device_size = '512MB'
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
# 8x8 configuration, 8 devices each with an 8-bit interface
|
|
|
|
device_bus_width = 8
|
|
|
|
|
|
|
|
# DDR3 is a BL8 device
|
|
|
|
burst_length = 8
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
|
2013-08-19 09:52:30 +02:00
|
|
|
device_rowbuffer_size = '1kB'
|
|
|
|
|
|
|
|
# 8x8 configuration, so 8 devices
|
|
|
|
devices_per_rank = 8
|
2013-01-31 13:49:14 +01:00
|
|
|
|
|
|
|
# Use two ranks
|
|
|
|
ranks_per_channel = 2
|
|
|
|
|
|
|
|
# DDR3 has 8 banks in all configurations
|
|
|
|
banks_per_rank = 8
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# 800 MHz
|
|
|
|
tCK = '1.25ns'
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
|
|
|
|
tBURST = '5ns'
|
|
|
|
|
|
|
|
# DDR3-1600 11-11-11
|
2013-01-31 13:49:14 +01:00
|
|
|
tRCD = '13.75ns'
|
|
|
|
tCL = '13.75ns'
|
|
|
|
tRP = '13.75ns'
|
2013-11-01 16:56:23 +01:00
|
|
|
tRAS = '35ns'
|
2014-05-10 00:58:49 +02:00
|
|
|
tRRD = '6ns'
|
|
|
|
tXAW = '30ns'
|
|
|
|
activation_limit = 4
|
|
|
|
tRFC = '260ns'
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
tWR = '15ns'
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# Greater of 4 CK or 7.5 ns
|
|
|
|
tWTR = '7.5ns'
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# Greater of 4 CK or 7.5 ns
|
|
|
|
tRTP = '7.5ns'
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
|
2014-05-10 00:58:49 +02:00
|
|
|
tRTW = '2.5ns'
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
|
|
|
|
tCS = '2.5ns'
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# <=85C, half for >85C
|
2013-01-31 13:49:14 +01:00
|
|
|
tREFI = '7.8us'
|
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
# Current values from datasheet
|
|
|
|
IDD0 = '75mA'
|
|
|
|
IDD2N = '50mA'
|
|
|
|
IDD3N = '57mA'
|
|
|
|
IDD4W = '165mA'
|
|
|
|
IDD4R = '187mA'
|
|
|
|
IDD5 = '220mA'
|
|
|
|
VDD = '1.5V'
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# A single DDR3-2133 x64 channel refining a selected subset of the
|
|
|
|
# options for the DDR-1600 configuration, based on the same DDR3-1600
|
|
|
|
# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
|
|
|
|
# consistent across the two configurations.
|
|
|
|
class DDR3_2133_x64(DDR3_1600_x64):
|
|
|
|
# 1066 MHz
|
|
|
|
tCK = '0.938ns'
|
|
|
|
|
|
|
|
# 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
|
|
|
|
tBURST = '3.752ns'
|
|
|
|
|
|
|
|
# DDR3-2133 14-14-14
|
|
|
|
tRCD = '13.09ns'
|
|
|
|
tCL = '13.09ns'
|
|
|
|
tRP = '13.09ns'
|
|
|
|
tRAS = '33ns'
|
|
|
|
tRRD = '5ns'
|
|
|
|
tXAW = '25ns'
|
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
# Current values from datasheet
|
|
|
|
IDD0 = '70mA'
|
|
|
|
IDD2N = '37mA'
|
|
|
|
IDD3N = '44mA'
|
|
|
|
IDD4W = '157mA'
|
|
|
|
IDD4R = '191mA'
|
|
|
|
IDD5 = '250mA'
|
|
|
|
VDD = '1.5V'
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# A single DDR4-2400 x64 channel (one command and address bus), with
|
2014-07-25 11:05:59 +02:00
|
|
|
# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
|
|
|
|
# in an 8x8 configuration.
|
2014-05-10 00:58:49 +02:00
|
|
|
class DDR4_2400_x64(DRAMCtrl):
|
2014-10-21 00:03:52 +02:00
|
|
|
# size of device
|
|
|
|
device_size = '512MB'
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# 8x8 configuration, 8 devices each with an 8-bit interface
|
|
|
|
device_bus_width = 8
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# DDR4 is a BL8 device
|
|
|
|
burst_length = 8
|
|
|
|
|
|
|
|
# Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
|
|
|
|
device_rowbuffer_size = '1kB'
|
|
|
|
|
|
|
|
# 8x8 configuration, so 8 devices
|
|
|
|
devices_per_rank = 8
|
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
# Match our DDR3 configurations which is dual rank
|
|
|
|
ranks_per_channel = 2
|
2014-05-10 00:58:49 +02:00
|
|
|
|
2014-09-20 23:18:21 +02:00
|
|
|
# DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
|
|
|
|
# Set to 4 for x4, x8 case
|
|
|
|
bank_groups_per_rank = 4
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# DDR4 has 16 banks (4 bank groups) in all
|
|
|
|
# configurations. Currently we do not capture the additional
|
|
|
|
# constraints incurred by the bank groups
|
|
|
|
banks_per_rank = 16
|
|
|
|
|
|
|
|
# 1200 MHz
|
|
|
|
tCK = '0.833ns'
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
|
2014-09-20 23:18:21 +02:00
|
|
|
# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
|
|
|
|
# With bank group architectures, tBURST represents the CAS-to-CAS
|
|
|
|
# delay for bursts to different bank groups (tCCD_S)
|
2014-05-10 00:58:49 +02:00
|
|
|
tBURST = '3.333ns'
|
2013-11-01 16:56:24 +01:00
|
|
|
|
2014-09-20 23:18:21 +02:00
|
|
|
# @2400 data rate, tCCD_L is 6 CK
|
|
|
|
# CAS-to-CAS delay for bursts to the same bank group
|
|
|
|
# tBURST is equivalent to tCCD_S; no explicit parameter required
|
|
|
|
# for CAS-to-CAS delay for bursts to different bank groups
|
|
|
|
tCCD_L = '5ns';
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# DDR4-2400 17-17-17
|
|
|
|
tRCD = '14.16ns'
|
|
|
|
tCL = '14.16ns'
|
|
|
|
tRP = '14.16ns'
|
|
|
|
tRAS = '32ns'
|
|
|
|
|
2014-09-20 23:18:21 +02:00
|
|
|
# RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
|
|
|
|
tRRD = '3.3ns'
|
|
|
|
|
|
|
|
# RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
|
|
|
|
tRRD_L = '4.9ns';
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
tXAW = '21ns'
|
2013-01-31 13:49:14 +01:00
|
|
|
activation_limit = 4
|
2014-07-25 11:05:59 +02:00
|
|
|
tRFC = '350ns'
|
2014-05-10 00:58:49 +02:00
|
|
|
|
|
|
|
tWR = '15ns'
|
|
|
|
|
|
|
|
# Here using the average of WTR_S and WTR_L
|
|
|
|
tWTR = '5ns'
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# Greater of 4 CK or 7.5 ns
|
|
|
|
tRTP = '7.5ns'
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
|
2014-05-10 00:58:49 +02:00
|
|
|
tRTW = '1.666ns'
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
|
|
|
|
tCS = '1.666ns'
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# <=85C, half for >85C
|
|
|
|
tREFI = '7.8us'
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
# Current values from datasheet
|
|
|
|
IDD0 = '64mA'
|
|
|
|
IDD02 = '4mA'
|
|
|
|
IDD2N = '50mA'
|
|
|
|
IDD3N = '67mA'
|
|
|
|
IDD3N2 = '3mA'
|
|
|
|
IDD4W = '180mA'
|
|
|
|
IDD4R = '160mA'
|
|
|
|
IDD5 = '192mA'
|
|
|
|
VDD = '1.2V'
|
|
|
|
VDD2 = '2.5V'
|
|
|
|
|
2013-05-30 18:54:14 +02:00
|
|
|
# A single LPDDR2-S4 x32 interface (one command/address bus), with
|
2014-07-25 11:05:59 +02:00
|
|
|
# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
|
|
|
|
# in a 1x32 configuration.
|
2014-03-23 16:12:12 +01:00
|
|
|
class LPDDR2_S4_1066_x32(DRAMCtrl):
|
2014-07-25 11:05:59 +02:00
|
|
|
# No DLL in LPDDR2
|
|
|
|
dll = False
|
|
|
|
|
2014-10-21 00:03:52 +02:00
|
|
|
# size of device
|
|
|
|
device_size = '512MB'
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
# 1x32 configuration, 1 device with a 32-bit interface
|
|
|
|
device_bus_width = 32
|
|
|
|
|
|
|
|
# LPDDR2_S4 is a BL4 and BL8 device
|
|
|
|
burst_length = 8
|
|
|
|
|
|
|
|
# Each device has a page (row buffer) size of 1KB
|
|
|
|
# (this depends on the memory density)
|
|
|
|
device_rowbuffer_size = '1kB'
|
|
|
|
|
|
|
|
# 1x32 configuration, so 1 device
|
|
|
|
devices_per_rank = 1
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2013-05-30 18:53:55 +02:00
|
|
|
# Use a single rank
|
|
|
|
ranks_per_channel = 1
|
2013-01-31 13:49:14 +01:00
|
|
|
|
|
|
|
# LPDDR2-S4 has 8 banks in all configurations
|
|
|
|
banks_per_rank = 8
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# 533 MHz
|
|
|
|
tCK = '1.876ns'
|
|
|
|
|
2013-01-31 13:49:14 +01:00
|
|
|
# Fixed at 15 ns
|
|
|
|
tRCD = '15ns'
|
|
|
|
|
|
|
|
# 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
|
|
|
|
tCL = '15ns'
|
|
|
|
|
2013-05-30 18:54:14 +02:00
|
|
|
# Pre-charge one bank 15 ns (all banks 18 ns)
|
|
|
|
tRP = '15ns'
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2013-11-01 16:56:23 +01:00
|
|
|
tRAS = '42ns'
|
2014-05-10 00:58:48 +02:00
|
|
|
tWR = '15ns'
|
2013-11-01 16:56:16 +01:00
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
tRTP = '7.5ns'
|
2014-05-10 00:58:48 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
# 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
|
|
|
|
# Note this is a BL8 DDR device.
|
|
|
|
# Requests larger than 32 bytes are broken down into multiple requests
|
2014-03-23 16:12:12 +01:00
|
|
|
# in the controller
|
2013-08-19 09:52:30 +02:00
|
|
|
tBURST = '7.5ns'
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2013-05-30 18:53:55 +02:00
|
|
|
# LPDDR2-S4, 4 Gbit
|
2013-01-31 13:49:14 +01:00
|
|
|
tRFC = '130ns'
|
|
|
|
tREFI = '3.9us'
|
|
|
|
|
|
|
|
# Irrespective of speed grade, tWTR is 7.5 ns
|
|
|
|
tWTR = '7.5ns'
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
|
2014-05-10 00:58:48 +02:00
|
|
|
tRTW = '3.75ns'
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
|
|
|
|
tCS = '3.75ns'
|
|
|
|
|
2013-11-01 16:56:24 +01:00
|
|
|
# Activate to activate irrespective of density and speed grade
|
|
|
|
tRRD = '10.0ns'
|
|
|
|
|
2013-05-30 18:53:55 +02:00
|
|
|
# Irrespective of density, tFAW is 50 ns
|
2013-01-31 13:49:14 +01:00
|
|
|
tXAW = '50ns'
|
|
|
|
activation_limit = 4
|
2013-04-22 19:20:33 +02:00
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
# Current values from datasheet
|
|
|
|
IDD0 = '15mA'
|
|
|
|
IDD02 = '70mA'
|
|
|
|
IDD2N = '2mA'
|
|
|
|
IDD2N2 = '30mA'
|
|
|
|
IDD3N = '2.5mA'
|
|
|
|
IDD3N2 = '30mA'
|
|
|
|
IDD4W = '10mA'
|
|
|
|
IDD4W2 = '190mA'
|
|
|
|
IDD4R = '3mA'
|
|
|
|
IDD4R2 = '220mA'
|
|
|
|
IDD5 = '40mA'
|
|
|
|
IDD52 = '150mA'
|
|
|
|
VDD = '1.8V'
|
|
|
|
VDD2 = '1.2V'
|
|
|
|
|
2013-05-30 18:54:14 +02:00
|
|
|
# A single WideIO x128 interface (one command and address bus), with
|
|
|
|
# default timings based on an estimated WIO-200 8 Gbit part.
|
2014-03-23 16:12:12 +01:00
|
|
|
class WideIO_200_x128(DRAMCtrl):
|
2014-07-25 11:05:59 +02:00
|
|
|
# No DLL for WideIO
|
|
|
|
dll = False
|
|
|
|
|
2014-10-21 00:03:52 +02:00
|
|
|
# size of device
|
|
|
|
device_size = '1024MB'
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
# 1x128 configuration, 1 device with a 128-bit interface
|
|
|
|
device_bus_width = 128
|
|
|
|
|
|
|
|
# This is a BL4 device
|
|
|
|
burst_length = 4
|
|
|
|
|
|
|
|
# Each device has a page (row buffer) size of 4KB
|
|
|
|
# (this depends on the memory density)
|
|
|
|
device_rowbuffer_size = '4kB'
|
|
|
|
|
|
|
|
# 1x128 configuration, so 1 device
|
|
|
|
devices_per_rank = 1
|
2013-04-22 19:20:33 +02:00
|
|
|
|
|
|
|
# Use one rank for a one-high die stack
|
|
|
|
ranks_per_channel = 1
|
|
|
|
|
|
|
|
# WideIO has 4 banks in all configurations
|
|
|
|
banks_per_rank = 4
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# 200 MHz
|
|
|
|
tCK = '5ns'
|
|
|
|
|
2013-04-22 19:20:33 +02:00
|
|
|
# WIO-200
|
|
|
|
tRCD = '18ns'
|
|
|
|
tCL = '18ns'
|
|
|
|
tRP = '18ns'
|
2013-11-01 16:56:23 +01:00
|
|
|
tRAS = '42ns'
|
2014-05-10 00:58:48 +02:00
|
|
|
tWR = '15ns'
|
2014-05-10 00:58:48 +02:00
|
|
|
# Read to precharge is same as the burst
|
|
|
|
tRTP = '20ns'
|
2013-04-22 19:20:33 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
# 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
|
|
|
|
# Note this is a BL4 SDR device.
|
2013-04-22 19:20:33 +02:00
|
|
|
tBURST = '20ns'
|
|
|
|
|
|
|
|
# WIO 8 Gb
|
|
|
|
tRFC = '210ns'
|
|
|
|
|
|
|
|
# WIO 8 Gb, <=85C, half for >85C
|
|
|
|
tREFI = '3.9us'
|
|
|
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|
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|
|
# Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
|
|
|
|
tWTR = '15ns'
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
|
2014-05-10 00:58:48 +02:00
|
|
|
tRTW = '10ns'
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default different rank bus delay to 2 CK, @200 MHz = 10 ns
|
|
|
|
tCS = '10ns'
|
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|
|
|
2013-11-01 16:56:24 +01:00
|
|
|
# Activate to activate irrespective of density and speed grade
|
|
|
|
tRRD = '10.0ns'
|
|
|
|
|
2013-04-22 19:20:33 +02:00
|
|
|
# Two instead of four activation window
|
|
|
|
tXAW = '50ns'
|
|
|
|
activation_limit = 2
|
2013-05-30 18:53:56 +02:00
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
# The WideIO specification does not provide current information
|
|
|
|
|
2013-05-30 18:54:14 +02:00
|
|
|
# A single LPDDR3 x32 interface (one command/address bus), with
|
2014-07-25 11:05:59 +02:00
|
|
|
# default timings based on a LPDDR3-1600 4 Gbit part (Micron
|
|
|
|
# EDF8132A1MC) in a 1x32 configuration.
|
2014-03-23 16:12:12 +01:00
|
|
|
class LPDDR3_1600_x32(DRAMCtrl):
|
2014-07-25 11:05:59 +02:00
|
|
|
# No DLL for LPDDR3
|
|
|
|
dll = False
|
|
|
|
|
2014-10-21 00:03:52 +02:00
|
|
|
# size of device
|
|
|
|
device_size = '512MB'
|
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
# 1x32 configuration, 1 device with a 32-bit interface
|
|
|
|
device_bus_width = 32
|
|
|
|
|
|
|
|
# LPDDR3 is a BL8 device
|
|
|
|
burst_length = 8
|
|
|
|
|
2013-11-01 16:56:30 +01:00
|
|
|
# Each device has a page (row buffer) size of 4KB
|
|
|
|
device_rowbuffer_size = '4kB'
|
2013-08-19 09:52:30 +02:00
|
|
|
|
|
|
|
# 1x32 configuration, so 1 device
|
|
|
|
devices_per_rank = 1
|
2013-05-30 18:53:56 +02:00
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
# Technically the datasheet is a dual-rank package, but for
|
|
|
|
# comparison with the LPDDR2 config we stick to a single rank
|
2013-05-30 18:53:56 +02:00
|
|
|
ranks_per_channel = 1
|
|
|
|
|
|
|
|
# LPDDR3 has 8 banks in all configurations
|
|
|
|
banks_per_rank = 8
|
|
|
|
|
2014-05-10 00:58:49 +02:00
|
|
|
# 800 MHz
|
|
|
|
tCK = '1.25ns'
|
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
tRCD = '18ns'
|
2013-05-30 18:53:56 +02:00
|
|
|
|
|
|
|
# 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
|
|
|
|
tCL = '15ns'
|
|
|
|
|
2013-11-01 16:56:23 +01:00
|
|
|
tRAS = '42ns'
|
2014-05-10 00:58:48 +02:00
|
|
|
tWR = '15ns'
|
2013-11-01 16:56:16 +01:00
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
# Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
|
|
|
|
tRTP = '7.5ns'
|
|
|
|
|
2014-07-25 11:05:59 +02:00
|
|
|
# Pre-charge one bank 18 ns (all banks 21 ns)
|
|
|
|
tRP = '18ns'
|
2013-05-30 18:53:56 +02:00
|
|
|
|
2013-08-19 09:52:30 +02:00
|
|
|
# 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
|
|
|
|
# Note this is a BL8 DDR device.
|
|
|
|
# Requests larger than 32 bytes are broken down into multiple requests
|
2014-03-23 16:12:12 +01:00
|
|
|
# in the controller
|
2013-08-19 09:52:30 +02:00
|
|
|
tBURST = '5ns'
|
2013-05-30 18:53:56 +02:00
|
|
|
|
|
|
|
# LPDDR3, 4 Gb
|
|
|
|
tRFC = '130ns'
|
|
|
|
tREFI = '3.9us'
|
|
|
|
|
|
|
|
# Irrespective of speed grade, tWTR is 7.5 ns
|
|
|
|
tWTR = '7.5ns'
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
|
2014-05-10 00:58:48 +02:00
|
|
|
tRTW = '2.5ns'
|
|
|
|
|
2014-09-20 23:17:57 +02:00
|
|
|
# Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
|
|
|
|
tCS = '2.5ns'
|
|
|
|
|
2013-11-01 16:56:24 +01:00
|
|
|
# Activate to activate irrespective of density and speed grade
|
|
|
|
tRRD = '10.0ns'
|
|
|
|
|
2013-05-30 18:53:56 +02:00
|
|
|
# Irrespective of size, tFAW is 50 ns
|
|
|
|
tXAW = '50ns'
|
|
|
|
activation_limit = 4
|
2014-07-25 11:05:59 +02:00
|
|
|
|
|
|
|
# Current values from datasheet
|
|
|
|
IDD0 = '8mA'
|
|
|
|
IDD02 = '60mA'
|
|
|
|
IDD2N = '0.8mA'
|
|
|
|
IDD2N2 = '26mA'
|
|
|
|
IDD3N = '2mA'
|
|
|
|
IDD3N2 = '34mA'
|
|
|
|
IDD4W = '2mA'
|
|
|
|
IDD4W2 = '190mA'
|
|
|
|
IDD4R = '2mA'
|
|
|
|
IDD4R2 = '230mA'
|
|
|
|
IDD5 = '28mA'
|
|
|
|
IDD52 = '150mA'
|
|
|
|
VDD = '1.8V'
|
|
|
|
VDD2 = '1.2V'
|
2014-12-02 12:07:32 +01:00
|
|
|
|
|
|
|
# A single GDDR5 x64 interface, with
|
|
|
|
# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
|
|
|
|
# H5GQ1H24AFR) in a 2x32 configuration.
|
|
|
|
class GDDR5_4000_x64(DRAMCtrl):
|
|
|
|
# size of device
|
|
|
|
device_size = '128MB'
|
|
|
|
|
|
|
|
# 2x32 configuration, 1 device with a 32-bit interface
|
|
|
|
device_bus_width = 32
|
|
|
|
|
|
|
|
# GDDR5 is a BL8 device
|
|
|
|
burst_length = 8
|
|
|
|
|
|
|
|
# Each device has a page (row buffer) size of 2Kbits (256Bytes)
|
|
|
|
device_rowbuffer_size = '256B'
|
|
|
|
|
|
|
|
# 2x32 configuration, so 2 devices
|
|
|
|
devices_per_rank = 2
|
|
|
|
|
|
|
|
# assume single rank
|
|
|
|
ranks_per_channel = 1
|
|
|
|
|
|
|
|
# GDDR5 has 4 bank groups
|
|
|
|
bank_groups_per_rank = 4
|
|
|
|
|
|
|
|
# GDDR5 has 16 banks with 4 bank groups
|
|
|
|
banks_per_rank = 16
|
|
|
|
|
|
|
|
# 1000 MHz
|
|
|
|
tCK = '1ns'
|
|
|
|
|
|
|
|
# 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
|
|
|
|
# Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
|
|
|
|
# 8 beats at 4000 MHz = 2 beats at 1000 MHz
|
|
|
|
# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
|
|
|
|
# With bank group architectures, tBURST represents the CAS-to-CAS
|
|
|
|
# delay for bursts to different bank groups (tCCD_S)
|
|
|
|
tBURST = '2ns'
|
|
|
|
|
|
|
|
# @1000MHz data rate, tCCD_L is 3 CK
|
|
|
|
# CAS-to-CAS delay for bursts to the same bank group
|
|
|
|
# tBURST is equivalent to tCCD_S; no explicit parameter required
|
|
|
|
# for CAS-to-CAS delay for bursts to different bank groups
|
|
|
|
tCCD_L = '3ns';
|
|
|
|
|
|
|
|
tRCD = '12ns'
|
|
|
|
|
|
|
|
# tCL is not directly found in datasheet and assumed equal tRCD
|
|
|
|
tCL = '12ns'
|
|
|
|
|
|
|
|
tRP = '12ns'
|
|
|
|
tRAS = '28ns'
|
|
|
|
|
|
|
|
# RRD_S (different bank group)
|
|
|
|
# RRD_S is 5.5 ns in datasheet.
|
|
|
|
# rounded to the next multiple of tCK
|
|
|
|
tRRD = '6ns'
|
|
|
|
|
|
|
|
# RRD_L (same bank group)
|
|
|
|
# RRD_L is 5.5 ns in datasheet.
|
|
|
|
# rounded to the next multiple of tCK
|
|
|
|
tRRD_L = '6ns'
|
|
|
|
|
|
|
|
tXAW = '23ns'
|
|
|
|
|
|
|
|
# tXAW < 4 x tRRD.
|
|
|
|
# Therefore, activation limit is set to 0
|
|
|
|
activation_limit = 0
|
|
|
|
|
|
|
|
tRFC = '65ns'
|
|
|
|
tWR = '12ns'
|
|
|
|
|
|
|
|
# Here using the average of WTR_S and WTR_L
|
|
|
|
tWTR = '5ns'
|
|
|
|
|
|
|
|
# Read-to-Precharge 2 CK
|
|
|
|
tRTP = '2ns'
|
|
|
|
|
|
|
|
# Assume 2 cycles
|
|
|
|
tRTW = '2ns'
|
|
|
|
|
|
|
|
# Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
|
|
|
|
tCS = '2ns'
|
|
|
|
tREFI = '3.9us'
|