2014-05-10 00:58:48 +02:00
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# Copyright (c) 2012-2014 ARM Limited
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2012-09-21 17:48:13 +02:00
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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2013-08-19 09:52:30 +02:00
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# Copyright (c) 2013 Amin Farmahini-Farahani
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# All rights reserved.
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#
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2012-09-21 17:48:13 +02:00
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Hansson
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# Ani Udipi
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from m5.params import *
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from AbstractMemory import *
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# Enum for memory scheduling algorithms, currently First-Come
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# First-Served and a First-Row Hit then First-Come First-Served
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class MemSched(Enum): vals = ['fcfs', 'frfcfs']
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2014-03-23 16:11:53 +01:00
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# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
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# channel, rank, bank, row and column, respectively, and going from
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# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
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# suitable for an open-page policy, optimising for sequential accesses
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# hitting in the open row. For a closed-page policy, RoCoRaBaCh
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# maximises parallelism.
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class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
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2012-09-21 17:48:13 +02:00
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2014-03-23 16:12:08 +01:00
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# Enum for the page policy, either open, open_adaptive, close, or
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# close_adaptive.
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class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
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'close_adaptive']
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2012-09-21 17:48:13 +02:00
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2014-03-23 16:12:12 +01:00
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# DRAMCtrl is a single-channel single-ported DRAM controller model
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2012-09-21 17:48:13 +02:00
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# that aims to model the most important system-level performance
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# effects of a DRAM without getting into too much detail of the DRAM
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# itself.
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2014-03-23 16:12:12 +01:00
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class DRAMCtrl(AbstractMemory):
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type = 'DRAMCtrl'
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cxx_header = "mem/dram_ctrl.hh"
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# single-ported on the system interface side, instantiate with a
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# bus in front of the controller for multiple ports
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port = SlavePort("Slave port")
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# the basic configuration of the controller architecture
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2014-03-23 16:12:10 +01:00
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write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
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2013-11-01 16:56:25 +01:00
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read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
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2014-03-23 16:12:01 +01:00
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# threshold in percent for when to forcefully trigger writes and
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# start emptying the write buffer
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write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
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2013-11-01 16:56:25 +01:00
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# threshold in percentage for when to start writes if the read
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# queue is empty
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write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
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# minimum write bursts to schedule before switching back to reads
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min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
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"switching to reads")
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2012-09-21 17:48:13 +02:00
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# scheduler, address map and page policy
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mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
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addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
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page_policy = Param.PageManage('open_adaptive', "Page management policy")
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2014-03-23 16:12:03 +01:00
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# enforce a limit on the number of accesses per row
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max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
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"closing");
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2013-05-30 18:54:12 +02:00
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# pipeline latency of the controller and PHY, split into a
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# frontend part and a backend part, with reads and writes serviced
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# by the queues only seeing the frontend contribution, and reads
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# serviced by the memory seeing the sum of the two
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static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
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static_backend_latency = Param.Latency("10ns", "Static backend latency")
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# the physical organisation of the DRAM
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device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
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"device/chip")
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burst_length = Param.Unsigned("Burst lenght (BL) in beats")
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device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
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"device/chip")
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devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
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2013-01-31 13:49:14 +01:00
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ranks_per_channel = Param.Unsigned("Number of ranks per channel")
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banks_per_rank = Param.Unsigned("Number of banks per rank")
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2013-03-01 19:20:22 +01:00
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# only used for the address mapping as the controller by
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# construction is a single channel and multiple controllers have
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# to be instantiated for a multi-channel configuration
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channels = Param.Unsigned(1, "Number of channels")
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2013-01-31 13:49:14 +01:00
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2012-09-21 17:48:13 +02:00
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# timing behaviour and constraints - all in nanoseconds
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# the amount of time in nanoseconds from issuing an activate command
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# to the data being available in the row buffer for a read/write
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2013-01-31 13:49:14 +01:00
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tRCD = Param.Latency("RAS to CAS delay")
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2012-09-21 17:48:13 +02:00
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# the time from issuing a read/write command to seeing the actual data
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2013-01-31 13:49:14 +01:00
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tCL = Param.Latency("CAS latency")
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# minimum time between a precharge and subsequent activate
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2013-01-31 13:49:14 +01:00
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tRP = Param.Latency("Row precharge time")
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2013-11-01 16:56:16 +01:00
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# minimum time between an activate and a precharge to the same row
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tRAS = Param.Latency("ACT to PRE delay")
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2014-05-10 00:58:48 +02:00
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# minimum time between a write data transfer and a precharge
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tWR = Param.Latency("Write recovery time")
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2014-05-10 00:58:48 +02:00
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# minimum time between a read and precharge command
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tRTP = Param.Latency("Read to precharge")
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2012-09-21 17:48:13 +02:00
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# time to complete a burst transfer, typically the burst length
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# divided by two due to the DDR bus, but by making it a parameter
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# it is easier to also evaluate SDR memories like WideIO.
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2013-08-19 09:52:30 +02:00
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# This parameter has to account for burst length.
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# Read/Write requests with data size larger than one full burst are broken
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2014-03-23 16:12:12 +01:00
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# down into multiple requests in the controller
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2013-01-31 13:49:14 +01:00
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tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
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# time taken to complete one refresh cycle (N rows in all banks)
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2013-01-31 13:49:14 +01:00
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tRFC = Param.Latency("Refresh cycle time")
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2012-09-21 17:48:13 +02:00
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# refresh command interval, how often a "ref" command needs
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# to be sent. It is 7.8 us for a 64ms refresh requirement
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2013-01-31 13:49:14 +01:00
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tREFI = Param.Latency("Refresh command interval")
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# write-to-read turn around penalty
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tWTR = Param.Latency("Write to read switching time")
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2014-05-10 00:58:48 +02:00
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# read-to-write turn around penalty, bus turnaround delay
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tRTW = Param.Latency("Read to write switching time")
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2013-11-01 16:56:24 +01:00
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# minimum row activate to row activate delay time
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tRRD = Param.Latency("ACT to ACT delay")
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2013-01-31 13:49:14 +01:00
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# time window in which a maximum number of activates are allowed
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# to take place, set to 0 to disable
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tXAW = Param.Latency("X activation window")
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activation_limit = Param.Unsigned("Max number of activates in window")
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2013-01-31 13:49:14 +01:00
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# Currently rolled into other params
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######################################################################
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2013-11-01 16:56:16 +01:00
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# tRC - assumed to be tRAS + tRP
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2012-09-21 17:48:13 +02:00
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2013-05-30 18:54:14 +02:00
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# A single DDR3 x64 interface (one command and address bus), with
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# default timings based on DDR3-1600 4 Gbit parts in an 8x8
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# configuration, which would amount to 4 Gbyte of memory.
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2014-03-23 16:12:12 +01:00
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class DDR3_1600_x64(DRAMCtrl):
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# 8x8 configuration, 8 devices each with an 8-bit interface
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device_bus_width = 8
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# DDR3 is a BL8 device
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burst_length = 8
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# Each device has a page (row buffer) size of 1KB
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2013-05-30 18:54:14 +02:00
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# (this depends on the memory density)
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2013-08-19 09:52:30 +02:00
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device_rowbuffer_size = '1kB'
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# 8x8 configuration, so 8 devices
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devices_per_rank = 8
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# Use two ranks
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ranks_per_channel = 2
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# DDR3 has 8 banks in all configurations
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banks_per_rank = 8
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2013-11-01 16:56:23 +01:00
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# DDR3-1600 11-11-11-28
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tRCD = '13.75ns'
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tCL = '13.75ns'
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tRP = '13.75ns'
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tRAS = '35ns'
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tWR = '15ns'
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tRTP = '7.5ns'
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2013-08-19 09:52:30 +02:00
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# 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
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# Note this is a BL8 DDR device.
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tBURST = '5ns'
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2013-05-30 18:54:14 +02:00
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# DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
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2013-01-31 13:49:14 +01:00
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tRFC = '300ns'
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# DDR3, <=85C, half for >85C
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tREFI = '7.8us'
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# Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
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tWTR = '7.5ns'
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2014-05-10 00:58:48 +02:00
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# Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
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tRTW = '2.5ns'
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2013-11-01 16:56:24 +01:00
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# Assume 5 CK for activate to activate for different banks
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tRRD = '6.25ns'
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2013-01-31 13:49:14 +01:00
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# With a 2kbyte page size, DDR3-1600 lands around 40 ns
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tXAW = '40ns'
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activation_limit = 4
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2014-03-23 16:11:56 +01:00
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# A single DDR3 x64 interface (one command and address bus), with
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# default timings based on DDR3-1333 4 Gbit parts in an 8x8
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# configuration, which would amount to 4 GByte of memory. This
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# configuration is primarily for comparing with DRAMSim2, and all the
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# parameters except ranks_per_channel are based on the DRAMSim2 config
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# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
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# to be manually set, depending on size of the memory to be
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# simulated. By default DRAMSim2 has 2048MB of memory with a single
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# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
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2014-03-23 16:12:12 +01:00
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class DDR3_1333_x64_DRAMSim2(DRAMCtrl):
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2014-03-23 16:11:56 +01:00
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# 8x8 configuration, 8 devices each with an 8-bit interface
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device_bus_width = 8
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# DDR3 is a BL8 device
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burst_length = 8
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# Each device has a page (row buffer) size of 1KB
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# (this depends on the memory density)
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device_rowbuffer_size = '1kB'
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# 8x8 configuration, so 8 devices
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devices_per_rank = 8
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# Use two ranks
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ranks_per_channel = 2
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# DDR3 has 8 banks in all configurations
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banks_per_rank = 8
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tRCD = '15ns'
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tCL = '15ns'
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tRP = '15ns'
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tRAS = '36ns'
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2014-05-10 00:58:48 +02:00
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tWR = '15ns'
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2014-05-10 00:58:48 +02:00
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tRTP = '7.5ns'
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2014-03-23 16:11:56 +01:00
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# 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.
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# Note this is a BL8 DDR device.
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tBURST = '6ns'
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tRFC = '160ns'
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# DDR3, <=85C, half for >85C
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tREFI = '7.8us'
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# Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns
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tWTR = '7.5ns'
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2014-05-10 00:58:48 +02:00
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# Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns
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tRTW = '3ns'
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2014-03-23 16:11:56 +01:00
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tRRD = '6.0ns'
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tXAW = '30ns'
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activation_limit = 4
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2013-05-30 18:54:14 +02:00
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# A single LPDDR2-S4 x32 interface (one command/address bus), with
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# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
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# configuration.
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2014-03-23 16:12:12 +01:00
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class LPDDR2_S4_1066_x32(DRAMCtrl):
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2013-08-19 09:52:30 +02:00
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# 1x32 configuration, 1 device with a 32-bit interface
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device_bus_width = 32
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# LPDDR2_S4 is a BL4 and BL8 device
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burst_length = 8
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# Each device has a page (row buffer) size of 1KB
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# (this depends on the memory density)
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device_rowbuffer_size = '1kB'
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# 1x32 configuration, so 1 device
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devices_per_rank = 1
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2013-01-31 13:49:14 +01:00
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2013-05-30 18:53:55 +02:00
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# Use a single rank
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ranks_per_channel = 1
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2013-01-31 13:49:14 +01:00
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# LPDDR2-S4 has 8 banks in all configurations
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banks_per_rank = 8
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# Fixed at 15 ns
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tRCD = '15ns'
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# 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
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tCL = '15ns'
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2013-05-30 18:54:14 +02:00
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# Pre-charge one bank 15 ns (all banks 18 ns)
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tRP = '15ns'
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2013-01-31 13:49:14 +01:00
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2013-11-01 16:56:23 +01:00
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tRAS = '42ns'
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2014-05-10 00:58:48 +02:00
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tWR = '15ns'
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2013-11-01 16:56:16 +01:00
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2014-05-10 00:58:48 +02:00
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# 6 CK read to precharge delay
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tRTP = '11.256ns'
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2013-08-19 09:52:30 +02:00
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# 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
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# Note this is a BL8 DDR device.
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# Requests larger than 32 bytes are broken down into multiple requests
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2014-03-23 16:12:12 +01:00
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# in the controller
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2013-08-19 09:52:30 +02:00
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tBURST = '7.5ns'
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2013-01-31 13:49:14 +01:00
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2013-05-30 18:53:55 +02:00
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# LPDDR2-S4, 4 Gbit
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2013-01-31 13:49:14 +01:00
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tRFC = '130ns'
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tREFI = '3.9us'
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# Irrespective of speed grade, tWTR is 7.5 ns
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tWTR = '7.5ns'
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2014-05-10 00:58:48 +02:00
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# Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns
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tRTW = '3.75ns'
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2013-11-01 16:56:24 +01:00
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# Activate to activate irrespective of density and speed grade
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tRRD = '10.0ns'
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2013-05-30 18:53:55 +02:00
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# Irrespective of density, tFAW is 50 ns
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2013-01-31 13:49:14 +01:00
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tXAW = '50ns'
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activation_limit = 4
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2013-04-22 19:20:33 +02:00
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2013-05-30 18:54:14 +02:00
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# A single WideIO x128 interface (one command and address bus), with
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# default timings based on an estimated WIO-200 8 Gbit part.
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2014-03-23 16:12:12 +01:00
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class WideIO_200_x128(DRAMCtrl):
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2013-08-19 09:52:30 +02:00
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# 1x128 configuration, 1 device with a 128-bit interface
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device_bus_width = 128
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# This is a BL4 device
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burst_length = 4
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# Each device has a page (row buffer) size of 4KB
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# (this depends on the memory density)
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device_rowbuffer_size = '4kB'
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# 1x128 configuration, so 1 device
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devices_per_rank = 1
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2013-04-22 19:20:33 +02:00
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# Use one rank for a one-high die stack
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ranks_per_channel = 1
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# WideIO has 4 banks in all configurations
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banks_per_rank = 4
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# WIO-200
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tRCD = '18ns'
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tCL = '18ns'
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tRP = '18ns'
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2013-11-01 16:56:23 +01:00
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tRAS = '42ns'
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2014-05-10 00:58:48 +02:00
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tWR = '15ns'
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2014-05-10 00:58:48 +02:00
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# Read to precharge is same as the burst
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tRTP = '20ns'
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2013-04-22 19:20:33 +02:00
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2013-08-19 09:52:30 +02:00
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# 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
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# Note this is a BL4 SDR device.
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2013-04-22 19:20:33 +02:00
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tBURST = '20ns'
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# WIO 8 Gb
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tRFC = '210ns'
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# WIO 8 Gb, <=85C, half for >85C
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tREFI = '3.9us'
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# Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
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tWTR = '15ns'
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2014-05-10 00:58:48 +02:00
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# Default read-to-write bus around to 2 CK, @200 MHz = 10 ns
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tRTW = '10ns'
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2013-11-01 16:56:24 +01:00
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# Activate to activate irrespective of density and speed grade
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tRRD = '10.0ns'
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2013-04-22 19:20:33 +02:00
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# Two instead of four activation window
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tXAW = '50ns'
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activation_limit = 2
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2013-05-30 18:53:56 +02:00
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2013-05-30 18:54:14 +02:00
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# A single LPDDR3 x32 interface (one command/address bus), with
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# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
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# configuration
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2014-03-23 16:12:12 +01:00
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class LPDDR3_1600_x32(DRAMCtrl):
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2013-08-19 09:52:30 +02:00
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# 1x32 configuration, 1 device with a 32-bit interface
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device_bus_width = 32
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# LPDDR3 is a BL8 device
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burst_length = 8
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2013-11-01 16:56:30 +01:00
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# Each device has a page (row buffer) size of 4KB
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device_rowbuffer_size = '4kB'
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2013-08-19 09:52:30 +02:00
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# 1x32 configuration, so 1 device
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devices_per_rank = 1
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2013-05-30 18:53:56 +02:00
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# Use a single rank
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ranks_per_channel = 1
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# LPDDR3 has 8 banks in all configurations
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banks_per_rank = 8
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# Fixed at 15 ns
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tRCD = '15ns'
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# 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
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tCL = '15ns'
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2013-11-01 16:56:23 +01:00
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tRAS = '42ns'
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2014-05-10 00:58:48 +02:00
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tWR = '15ns'
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2013-11-01 16:56:16 +01:00
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2014-05-10 00:58:48 +02:00
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# Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
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tRTP = '7.5ns'
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2013-05-30 18:54:14 +02:00
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# Pre-charge one bank 15 ns (all banks 18 ns)
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tRP = '15ns'
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2013-05-30 18:53:56 +02:00
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2013-08-19 09:52:30 +02:00
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# 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
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# Note this is a BL8 DDR device.
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# Requests larger than 32 bytes are broken down into multiple requests
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2014-03-23 16:12:12 +01:00
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# in the controller
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2013-08-19 09:52:30 +02:00
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tBURST = '5ns'
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2013-05-30 18:53:56 +02:00
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# LPDDR3, 4 Gb
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tRFC = '130ns'
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tREFI = '3.9us'
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# Irrespective of speed grade, tWTR is 7.5 ns
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tWTR = '7.5ns'
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2014-05-10 00:58:48 +02:00
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# Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
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tRTW = '2.5ns'
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2013-11-01 16:56:24 +01:00
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# Activate to activate irrespective of density and speed grade
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tRRD = '10.0ns'
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2013-05-30 18:53:56 +02:00
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# Irrespective of size, tFAW is 50 ns
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tXAW = '50ns'
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activation_limit = 4
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