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mem: Clarify unit of DRAM controller buffer size

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This commit is contained in:
Andreas Hansson 2014-11-14 03:53:48 -05:00
parent 4583a5114a
commit 9ffe0e7ba6
1 changed files with 4 additions and 1 deletions
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5
src/mem/DRAMCtrl.py
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@ -71,7 +71,10 @@ class DRAMCtrl(AbstractMemory):
# bus in front of the controller for multiple ports
port = SlavePort("Slave port")
# the basic configuration of the controller architecture
# the basic configuration of the controller architecture, note
# that each entry corresponds to a burst for the specific DRAM
# configuration (e.g. x32 with burst length 8 is 32 bytes) and not
# the cacheline size or request/packet size
write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
read_buffer_size = Param.Unsigned(32, "Number of read queue entries")