2011-02-07 10:23:16 +01:00
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---------- Begin Simulation Statistics ----------
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2012-01-10 16:59:01 +01:00
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sim_seconds 5.112043 # Number of seconds simulated
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sim_ticks 5112043255000 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-02-07 10:23:16 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-09-11 16:34:40 +02:00
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host_inst_rate 1011485 # Simulator instruction rate (inst/s)
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host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 25877843451 # Simulator tick rate (ticks/s)
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host_mem_usage 397304 # Number of bytes of host memory used
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host_seconds 197.55 # Real time elapsed on the host
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2012-07-23 03:31:24 +02:00
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sim_insts 199813914 # Number of instructions simulated
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sim_ops 409133298 # Number of ops (including micro ops) simulated
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2012-06-29 17:19:03 +02:00
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system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory
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system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory
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system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory
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system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory
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system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s)
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2012-10-15 14:08:06 +02:00
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system.cpu.l2cache.replacements 106561 # number of replacements
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system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits
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system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
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system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits
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system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses
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system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses
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system.cpu.l2cache.overall_misses::total 179910 # number of overall misses
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system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses
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system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks
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|
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system.cpu.l2cache.writebacks::total 98533 # number of writebacks
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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2012-01-10 16:59:01 +01:00
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system.iocache.replacements 47570 # number of replacements
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system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
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2011-11-05 21:32:23 +01:00
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|
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system.iocache.total_refs 0 # Total number of references to valid blocks.
|
2012-01-10 16:59:01 +01:00
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|
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system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
|
2011-02-07 10:23:16 +01:00
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system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
2012-01-10 16:59:01 +01:00
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|
|
system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
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2012-02-12 23:07:43 +01:00
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|
|
system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
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|
|
|
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system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
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|
|
|
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system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
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|
|
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
|
2012-01-10 16:59:01 +01:00
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|
|
system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
2011-11-05 21:32:23 +01:00
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|
|
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
2012-02-12 23:07:43 +01:00
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|
|
system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
|
2012-01-10 16:59:01 +01:00
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|
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system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
|
2012-02-12 23:07:43 +01:00
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|
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system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
|
2012-01-10 16:59:01 +01:00
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|
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system.iocache.overall_misses::total 47625 # number of overall misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
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|
|
system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
2011-11-05 21:32:23 +01:00
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|
|
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
|
|
|
|
system.iocache.writebacks::total 46667 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
|
|
|
|
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
2011-11-05 21:32:23 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
2011-02-07 10:23:16 +01:00
|
|
|
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.numCycles 10224086531 # number of cpu cycles simulated
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-07-23 03:31:24 +02:00
|
|
|
system.cpu.committedInsts 199813914 # Number of instructions committed
|
|
|
|
|
system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
|
|
|
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
2012-07-23 03:31:24 +02:00
|
|
|
system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu.num_int_insts 374297264 # number of integer instructions
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.num_fp_insts 0 # number of float instructions
|
2012-09-11 16:34:40 +02:00
|
|
|
system.cpu.num_int_register_reads 915470380 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 480331069 # number of times the integer registers were written
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
|
|
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.num_mem_refs 35626517 # number of memory refs
|
|
|
|
|
system.cpu.num_load_insts 27217782 # Number of load instructions
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.num_store_insts 8408735 # Number of store instructions
|
2012-07-23 03:31:24 +02:00
|
|
|
system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles
|
|
|
|
|
system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
|
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.icache.replacements 790793 # number of replacements
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
|
2012-07-23 03:31:24 +02:00
|
|
|
system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks.
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks.
|
2012-07-23 03:31:24 +02:00
|
|
|
system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
|
2012-07-23 03:31:24 +02:00
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 243365779 # number of overall hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 791312 # number of overall misses
|
2012-07-23 03:31:24 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.itb_walker_cache.replacements 3335 # number of replacements
|
|
|
|
|
system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use
|
|
|
|
|
system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits
|
|
|
|
|
system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks
|
|
|
|
|
system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dtb_walker_cache.replacements 7598 # number of replacements
|
|
|
|
|
system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.replacements 1621273 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks.
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 20139960 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-06-29 17:19:03 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 1534981 # number of writebacks
|
2011-11-05 21:32:23 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-07 10:23:16 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
