2006-10-06 10:23:27 +02:00
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|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2012-10-30 14:35:32 +01:00
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|
|
sim_seconds 0.000020 # Number of seconds simulated
|
2012-11-02 17:50:06 +01:00
|
|
|
sim_ticks 19857000 # Number of ticks simulated
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|
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|
|
final_tick 19857000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2006-10-06 10:23:27 +02:00
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|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2012-11-02 17:50:06 +01:00
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|
|
host_inst_rate 50642 # Simulator instruction rate (inst/s)
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|
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|
host_op_rate 50640 # Simulator op (including micro ops) rate (op/s)
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|
host_tick_rate 78893380 # Simulator tick rate (ticks/s)
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|
|
host_mem_usage 214784 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 0.25 # Real time elapsed on the host
|
2012-08-15 16:38:05 +02:00
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|
|
sim_insts 12745 # Number of instructions simulated
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|
|
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|
sim_ops 12745 # Number of ops (including micro ops) simulated
|
2012-11-02 17:50:06 +01:00
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|
|
system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory
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|
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|
|
system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory
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|
system.physmem.bytes_read::total 62208 # Number of bytes read from this memory
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|
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|
|
system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory
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|
system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory
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|
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|
|
system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory
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|
|
|
|
system.physmem.num_reads::total 972 # Number of read requests responded to by this memory
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|
|
|
|
system.physmem.bw_read::cpu.inst 2004733847 # Total read bandwidth from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_read::cpu.data 1128065670 # Total read bandwidth from this memory (bytes/s)
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|
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|
|
system.physmem.bw_read::total 3132799517 # Total read bandwidth from this memory (bytes/s)
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|
|
system.physmem.bw_inst_read::cpu.inst 2004733847 # Instruction read bandwidth from this memory (bytes/s)
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|
system.physmem.bw_inst_read::total 2004733847 # Instruction read bandwidth from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_total::cpu.inst 2004733847 # Total bandwidth to/from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_total::cpu.data 1128065670 # Total bandwidth to/from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_total::total 3132799517 # Total bandwidth to/from this memory (bytes/s)
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|
|
|
|
system.physmem.readReqs 972 # Total number of read requests seen
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeReqs 0 # Total number of write requests seen
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.cpureqs 972 # Reqs generatd by CPU via cache - shady
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|
|
|
|
system.physmem.bytesRead 62208 # Total number of bytes read from memory
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.bytesConsumedRd 62208 # bytesRead derated as per pkt->getSize()
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
|
|
|
|
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
|
|
|
|
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
|
|
|
|
system.physmem.perBankRdReqs::0 73 # Track reads on a per bank basis
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.perBankRdReqs::1 51 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::2 70 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::3 122 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::7 74 # Track reads on a per bank basis
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::11 100 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::13 26 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::15 76 # Track reads on a per bank basis
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
|
|
|
|
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.totGap 19816500 # Total gap between requests
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.readPktSize::6 972 # Categorize read packet sizes
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
|
|
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|
|
system.physmem.rdQLenPdf::1 318 # What read queue length does an incoming req see
|
|
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|
|
system.physmem.rdQLenPdf::2 215 # What read queue length does an incoming req see
|
|
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|
system.physmem.rdQLenPdf::3 98 # What read queue length does an incoming req see
|
|
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|
|
system.physmem.rdQLenPdf::4 50 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see
|
2012-10-30 14:35:32 +01:00
|
|
|
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.totQLat 11651972 # Total cycles spent in queuing delays
|
|
|
|
|
system.physmem.totMemAccLat 34145972 # Sum of mem lat for all requests
|
|
|
|
|
system.physmem.totBusLat 3888000 # Total cycles spent in databus access
|
|
|
|
|
system.physmem.totBankLat 18606000 # Total cycles spent in bank access
|
|
|
|
|
system.physmem.avgQLat 11987.63 # Average queueing delay per request
|
|
|
|
|
system.physmem.avgBankLat 19141.98 # Average bank access latency per request
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.avgMemAccLat 35129.60 # Average memory access latency
|
|
|
|
|
system.physmem.avgRdBW 3132.80 # Average achieved read bandwidth in MB/s
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.avgConsumedRdBW 3132.80 # Average consumed read bandwidth in MB/s
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
|
|
|
|
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.busUtil 19.58 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.avgRdQLen 1.72 # Average read queue length over time
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.readRowHits 733 # Number of row buffer hits during reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.readRowHitRate 75.41 # Row buffer hit rate for reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.avgGap 20387.35 # Average gap between requests
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.read_hits 4359 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 96 # DTB read misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.read_accesses 4455 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_hits 2014 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 72 # DTB write misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.write_accesses 2086 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.data_hits 6373 # DTB hits
|
|
|
|
|
system.cpu.dtb.data_misses 168 # DTB misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.data_accesses 6541 # DTB accesses
|
|
|
|
|
system.cpu.itb.fetch_hits 5250 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 57 # ITB misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.itb.fetch_accesses 5307 # ITB accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload0.num_syscalls 17 # Number of system calls
|
|
|
|
|
system.cpu.workload1.num_syscalls 17 # Number of system calls
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.numCycles 39715 # number of cpu cycles simulated
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.BPredUnit.lookups 6348 # Number of BP lookups
|
|
|
|
|
system.cpu.BPredUnit.condPredicted 3569 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.BPredUnit.condIncorrect 1446 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.BPredUnit.BTBLookups 4530 # Number of BTB lookups
|
|
|
|
|
system.cpu.BPredUnit.BTBHits 874 # Number of BTB hits
|
2009-03-07 23:30:55 +01:00
|
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.BPredUnit.usedRAS 898 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.BPredUnit.RASInCorrect 184 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 1539 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 35371 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 6348 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 1772 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 5994 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 1779 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.CacheLines 5250 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 858 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 26295 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 1.345161 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.748208 # Number of instructions fetched each cycle (Total)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.fetch.rateDist::0 20301 77.20% 77.20% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 545 2.07% 79.28% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 388 1.48% 80.75% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 414 1.57% 82.33% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 431 1.64% 83.97% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 401 1.53% 85.49% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 440 1.67% 87.16% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 561 2.13% 89.30% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 2814 10.70% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.fetch.rateDist::total 26295 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.159839 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 0.890621 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 37128 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 7028 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 5161 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 465 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 2623 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 533 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 326 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 31237 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 663 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 2623 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 37789 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 3807 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 1133 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 4855 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 2198 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 28851 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.LSQFullEvents 2210 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RenamedOperands 21669 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 35547 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 35513 # Number of integer rename lookups
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.rename.UndoneMaps 12529 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 51 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 6010 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 2907 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.memDep1.insertedLoads 2775 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep1.insertedStores 1297 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.iqInstsAdded 25429 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 70 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 21088 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 11668 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 7282 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 26295 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 0.801978 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.371425 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::0 17201 65.42% 65.42% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 3228 12.28% 77.69% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 2604 9.90% 87.59% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 1566 5.96% 93.55% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 907 3.45% 97.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 493 1.87% 98.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 226 0.86% 99.73% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 55 0.21% 99.94% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 15 0.06% 100.00% # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 26295 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 117 60.31% 65.98% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 66 34.02% 100.00% # attempts to use FU when none available
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 6973 65.93% 65.95% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 2492 23.56% 89.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 1106 10.46% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 10576 # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type_1::IntAlu 7011 66.70% 66.71% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.72% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::MemRead 2403 22.86% 89.60% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::MemWrite 1093 10.40% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type_1::total 10512 # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type::IntAlu 13984 66.31% 66.33% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::IntMult 2 0.01% 66.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::IntDiv 0 0.00% 66.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::FloatMult 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdMult 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdShift 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::MemRead 4895 23.21% 89.57% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::MemWrite 2199 10.43% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type::total 21088 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 0.530983 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_cnt::1 100 # FU busy when requested
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.iq.fu_busy_cnt::total 194 # FU busy when requested
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.fu_busy_rate::0 0.004458 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.fu_busy_rate::1 0.004742 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.fu_busy_rate::total 0.009200 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 68733 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 37173 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 18381 # Number of integer instruction queue wakeup accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.int_alu_accesses 21256 # Number of integer alu accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1724 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 355 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread1.squashedLoads 1592 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread1.squashedStores 432 # Number of stores squashed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread1.cacheBlocked 238 # Number of times an access to memory failed due to the cache being blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 2623 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 887 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 25678 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 656 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 5682 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 2660 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 70 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 31 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 235 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1060 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 1295 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 19629 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts::0 2279 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts::1 2190 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts::total 4469 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1459 # Number of squashed instructions skipped in execute
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.exec_nop::0 110 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_nop::1 69 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_nop::total 179 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs::0 3341 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_refs::1 3226 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_refs::total 6567 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches::0 1545 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_branches::1 1563 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_branches::total 3108 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores::0 1062 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_stores::1 1036 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_stores::total 2098 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.494247 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent::0 9363 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_sent::1 9308 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_sent::total 18671 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count::0 9223 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_count::1 9178 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_count::total 18401 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers::0 4724 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_producers::1 4736 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_producers::total 9460 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers::0 6156 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_consumers::1 6184 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_consumers::total 12340 # num instructions consuming a value
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.wb_rate::0 0.232230 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_rate::1 0.231097 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_rate::total 0.463326 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout::0 0.767381 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_fanout::1 0.765847 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_fanout::total 0.766613 # average fanout of values written-back
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 12926 # The number of squashed insts skipped by commit
|
2006-10-06 10:23:27 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.branchMispredicts 1134 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 26218 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.487413 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.275738 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 20568 78.45% 78.45% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 2989 11.40% 89.85% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 1062 4.05% 93.90% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 514 1.96% 95.86% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 342 1.30% 97.17% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 238 0.91% 98.07% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 201 0.77% 98.84% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 72 0.27% 99.12% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 232 0.88% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 26218 # Number of insts commited each cycle
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.refs::0 2048 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.refs::1 2048 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.refs::total 4096 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads::0 1183 # Number of loads committed
|
|
|
|
|
system.cpu.commit.loads::1 1183 # Number of loads committed
|
|
|
|
|
system.cpu.commit.loads::total 2366 # Number of loads committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.membars::0 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.membars::1 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.membars::total 0 # Number of memory barriers committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.branches::0 1050 # Number of branches committed
|
|
|
|
|
system.cpu.commit.branches::1 1050 # Number of branches committed
|
|
|
|
|
system.cpu.commit.branches::total 2100 # Number of branches committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
|
|
|
|
|
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
|
|
|
|
|
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.rob.rob_reads 123093 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 54044 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 13420 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.cpi::0 6.232737 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi::1 6.231759 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 3.116124 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc::0 0.160443 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc::1 0.160468 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.320911 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 24691 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 13868 # number of integer regfile writes
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.replacements::0 7 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.replacements::1 0 # number of replacements
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.replacements::total 7 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 306.891389 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 4214 # Total number of references to valid blocks.
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.avg_refs 6.742400 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 306.891389 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.149849 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.149849 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 4214 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 4214 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 4214 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 4214 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 4214 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 4214 # number of overall hits
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1030 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 1030 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 1030 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 1030 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 1030 # number of overall misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56718997 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 56718997 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 56718997 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 56718997 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 56718997 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 56718997 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 5244 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 5244 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 5244 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 5244 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 5244 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 5244 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196415 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.196415 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.196415 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.196415 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.196415 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.196415 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.987379 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 55066.987379 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 55066.987379 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 55066.987379 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 2360 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 42.142857 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2006-10-07 17:32:10 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 405 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 405 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 405 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 405 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 405 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 625 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38021997 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 38021997 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38021997 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 38021997 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38021997 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 38021997 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119184 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.119184 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.119184 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60835.195200 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60835.195200 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements::0 0 # number of replacements
|
|
|
|
|
system.cpu.dcache.replacements::1 0 # number of replacements
|
|
|
|
|
system.cpu.dcache.replacements::total 0 # number of replacements
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.tagsinuse 210.613846 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 4387 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 349 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 12.570201 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 210.613846 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.051419 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 4387 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 1035 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 685 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 685 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 685 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 685 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14127500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 14127500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8703496 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8703496 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22830996 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 22830996 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22830996 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 22830996 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055255 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements::0 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.replacements::1 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.replacements::total 0 # number of replacements
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 425.528507 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 826 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.003632 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 307.423460 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 118.105047 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.009382 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.003604 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.012986 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 622 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 826 # number of ReadReq misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 622 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 350 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 972 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 622 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 350 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 972 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37362500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13955000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 51317500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8555000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8555000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 37362500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 22510000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 59872500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 37362500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 22510000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 59872500 # number of overall miss cycles
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 625 # number of ReadReq accesses(hits+misses)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 829 # number of ReadReq accesses(hits+misses)
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 625 # number of demand (read+write) accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 350 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 975 # number of demand (read+write) accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 625 # number of overall (read+write) accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 350 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 975 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995200 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.996381 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995200 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.996923 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995200 # miss rate for overall accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.996923 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60068.327974 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68406.862745 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 62127.723971 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58595.890411 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58595.890411 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60068.327974 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64314.285714 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 61597.222222 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60068.327974 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64314.285714 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 61597.222222 # average overall miss latency
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2006-10-07 17:32:10 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 622 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 622 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 972 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 972 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29639174 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11445162 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41084336 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6748648 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6748648 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29639174 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18193810 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 47832984 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29639174 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18193810 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 47832984 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995200 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996381 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995200 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.996923 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995200 # mshr miss rate for overall accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.996923 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47651.405145 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56103.735294 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49738.905569 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46223.616438 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46223.616438 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47651.405145 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51982.314286 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49210.888889 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47651.405145 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51982.314286 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49210.888889 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-06 10:23:27 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
