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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

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Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- Begin Simulation Statistics ----------
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
sim_seconds 1.854350 # Number of seconds simulated
sim_ticks 1854349611000 # Number of ticks simulated
final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
host_inst_rate 135035 # Simulator instruction rate (inst/s)
host_op_rate 135035 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4724741522 # Simulator tick rate (ticks/s)
host_mem_usage 327760 # Number of bytes of host memory used
host_seconds 392.48 # Real time elapsed on the host
sim_insts 52998188 # Number of instructions simulated
sim_ops 52998188 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
system.physmem.bytes_read::total 28499904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7518592 # Number of bytes written to this memory
system.physmem.bytes_written::total 7518592 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
system.physmem.num_reads::total 445311 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 117478 # Number of write requests responded to by this memory
system.physmem.num_writes::total 117478 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 521567 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13417345 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1430306 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15369218 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 521567 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 521567 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4054571 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4054571 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4054571 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 521567 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13417345 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1430306 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19423789 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 445311 # Total number of read requests seen
system.physmem.writeReqs 117478 # Total number of write requests seen
system.physmem.cpureqs 564077 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28499904 # Total number of bytes read from memory
system.physmem.bytesWritten 7518592 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28499904 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7518592 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::0 28171 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 27744 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 27861 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 28325 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 28126 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 27859 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 27840 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 27508 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 27634 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 27843 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 27857 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 27753 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 27753 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 27902 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7651 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7405 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7296 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 6891 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7793 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7560 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7306 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7405 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7055 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7167 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 7397 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7475 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7357 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7329 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.numWrRetry 554 # Number of times wr buffer was full causing retry
system.physmem.totGap 1854344226000 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.readPktSize::6 445311 # Categorize read packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.writePktSize::6 118032 # categorize write packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 175 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::0 331896 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 65179 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 18458 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 6410 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2875 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2427 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1797 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2003 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1654 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1944 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1608 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::12 1627 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1778 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1217 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1424 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 888 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.wrQLenPdf::0 3926 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4929 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4979 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5052 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5068 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.totQLat 6253510302 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13461286302 # Sum of mem lat for all requests
system.physmem.totBusLat 1781012000 # Total cycles spent in databus access
system.physmem.totBankLat 5426764000 # Total cycles spent in bank access
system.physmem.avgQLat 14044.85 # Average queueing delay per request
system.physmem.avgBankLat 12188.05 # Average bank access latency per request
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgBusLat 4000.00 # Average bus latency per request
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.avgMemAccLat 30232.89 # Average memory access latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.avgWrQLen 11.07 # Average write queue length over time
system.physmem.readRowHits 425296 # Number of row buffer hits during reads
system.physmem.writeRowHits 76454 # Number of row buffer hits during writes
system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 65.08 # Row buffer hit rate for writes
system.physmem.avgGap 3294919.10 # Average gap between requests
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.replacements 41685 # number of replacements
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.iocache.tagsinuse 1.265413 # Cycle average of tags in use
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.iocache.warmup_cycle 1704469740000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.079088 # Average percentage of cache occupancy
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.overall_misses::total 41725 # number of overall misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 9494924806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 9494924806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 9515852804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 9515852804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 9515852804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 9515852804 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228507.046737 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 228507.046737 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 228061.181642 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 228061.181642 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 189089 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.iocache.blocked::no_mshrs 22862 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 8.270886 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7332138561 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 7332138561 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 7344069561 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 7344069561 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 7344069561 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 7344069561 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176456.934949 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 176456.934949 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.read_hits 9959916 # DTB read hits
system.cpu.dtb.read_misses 41524 # DTB read misses
system.cpu.dtb.read_acv 557 # DTB read access violations
system.cpu.dtb.read_accesses 942700 # DTB read accesses
system.cpu.dtb.write_hits 6603148 # DTB write hits
system.cpu.dtb.write_misses 10669 # DTB write misses
system.cpu.dtb.write_acv 409 # DTB write access violations
system.cpu.dtb.write_accesses 338186 # DTB write accesses
system.cpu.dtb.data_hits 16563064 # DTB hits
system.cpu.dtb.data_misses 52193 # DTB misses
system.cpu.dtb.data_acv 966 # DTB access violations
system.cpu.dtb.data_accesses 1280886 # DTB accesses
system.cpu.itb.fetch_hits 1308562 # ITB hits
system.cpu.itb.fetch_misses 36917 # ITB misses
system.cpu.itb.fetch_acv 1051 # ITB acv
system.cpu.itb.fetch_accesses 1345479 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.numCycles 108866981 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.BPredUnit.lookups 13878911 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11630816 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 403232 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 9482716 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 5833581 # Number of BTB hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.BPredUnit.usedRAS 911561 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 38998 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 28184398 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 70994195 # Number of instructions fetch has processed
system.cpu.fetch.Branches 13878911 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 6745142 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 13311939 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2031019 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 37417570 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 32583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 255429 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 315513 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 8617973 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 269432 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 80827249 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.878345 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.221663 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.fetch.rateDist::0 67515310 83.53% 83.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 859289 1.06% 84.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1709305 2.11% 86.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 824937 1.02% 87.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2774546 3.43% 91.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 565272 0.70% 91.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 652347 0.81% 92.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1007085 1.25% 93.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 4919158 6.09% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.fetch.rateDist::total 80827249 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.127485 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.652119 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 29306094 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 37119542 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 12159527 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 975132 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1266953 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 590499 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 43097 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 69660736 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 130298 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1266953 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 30443941 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 13656496 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 19805604 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 11392846 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4261407 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 65802441 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 6765 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 504009 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1491914 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 43932847 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 79894315 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 79415060 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 479255 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 38191269 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 5741570 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1687796 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 244874 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12188114 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 10482106 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6925475 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1313213 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 855117 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 58302952 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2055207 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 56888280 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 110464 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 6988476 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3659625 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1390229 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 80827249 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.703826 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.364551 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.issued_per_cycle::0 56119293 69.43% 69.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 10851228 13.43% 82.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5175866 6.40% 89.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3389461 4.19% 93.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 2645582 3.27% 96.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1466047 1.81% 98.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 750476 0.93% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 332850 0.41% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 96446 0.12% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.issued_per_cycle::total 80827249 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.fu_full::IntAlu 91026 11.51% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 373270 47.20% 58.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 326472 41.29% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 38768679 68.15% 68.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 61732 0.11% 68.27% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::MemRead 10391331 18.27% 86.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 6681118 11.74% 98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 948891 1.67% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::total 56888280 # Type of FU issued
system.cpu.iq.rate 0.522549 # Inst issue rate
system.cpu.iq.fu_busy_cnt 790768 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013900 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 194812399 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 67023826 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 55617934 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 692641 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 336620 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 327880 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 57310327 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 361435 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 598219 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 1386761 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3497 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 544022 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 17955 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 206298 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.iewSquashCycles 1266953 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 9965004 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 682330 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 63888752 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 694377 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 10482106 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 6925475 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1810071 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 511236 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 18909 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 204344 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 411597 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 615941 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 56420713 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 10029634 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 467566 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.exec_nop 3530593 # number of nop insts executed
system.cpu.iew.exec_refs 16658677 # number of memory reference insts executed
system.cpu.iew.exec_branches 8937468 # Number of branches executed
system.cpu.iew.exec_stores 6629043 # Number of stores executed
system.cpu.iew.exec_rate 0.518254 # Inst execution rate
system.cpu.iew.wb_sent 56060470 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 55945814 # cumulative count of insts written-back
system.cpu.iew.wb_producers 27785553 # num instructions producing a value
system.cpu.iew.wb_consumers 37633865 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.wb_rate 0.513891 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.738313 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.commitSquashedInsts 7580888 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 664978 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 571532 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 79560296 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.706241 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.634825 # Number of insts commited each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.committed_per_cycle::0 58754657 73.85% 73.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 8628270 10.84% 84.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4624578 5.81% 90.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2529268 3.18% 93.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1515738 1.91% 95.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 609533 0.77% 96.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 524421 0.66% 97.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 524312 0.66% 97.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1849519 2.32% 100.00% # Number of insts commited each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.committed_per_cycle::total 79560296 # Number of insts commited each cycle
system.cpu.commit.committedInsts 56188709 # Number of instructions committed
system.cpu.commit.committedOps 56188709 # Number of ops (including micro ops) committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.refs 15476798 # Number of memory references committed
system.cpu.commit.loads 9095345 # Number of loads committed
system.cpu.commit.membars 226320 # Number of memory barriers committed
system.cpu.commit.branches 8447896 # Number of branches committed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.int_insts 52034633 # Number of committed integer instructions.
system.cpu.commit.function_calls 740447 # Number of function calls committed.
system.cpu.commit.bw_lim_events 1849519 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.rob.rob_reads 141230883 # The number of ROB reads
system.cpu.rob.rob_writes 128808067 # The number of ROB writes
system.cpu.timesIdled 1177683 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 28039732 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3599825806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 52998188 # Number of Instructions Simulated
system.cpu.committedOps 52998188 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 52998188 # Number of Instructions Simulated
system.cpu.cpi 2.054164 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.054164 # CPI: Total CPI of All Threads
system.cpu.ipc 0.486816 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.486816 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 73962724 # number of integer regfile reads
system.cpu.int_regfile_writes 40347354 # number of integer regfile writes
system.cpu.fp_regfile_reads 166024 # number of floating regfile reads
system.cpu.fp_regfile_writes 167429 # number of floating regfile writes
system.cpu.misc_regfile_reads 1993125 # number of misc regfile reads
system.cpu.misc_regfile_writes 947074 # number of misc regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.replacements 1012720 # number of replacements
system.cpu.icache.tagsinuse 510.299473 # Cycle average of tags in use
system.cpu.icache.total_refs 7548318 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1013228 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.449772 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 20110483000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.299473 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996679 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996679 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7548319 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7548319 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7548319 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7548319 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7548319 # number of overall hits
system.cpu.icache.overall_hits::total 7548319 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1069652 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1069652 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1069652 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1069652 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1069652 # number of overall misses
system.cpu.icache.overall_misses::total 1069652 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14542561994 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14542561994 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14542561994 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14542561994 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14542561994 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14542561994 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 8617971 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 8617971 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 8617971 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 8617971 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 8617971 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 8617971 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124119 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.124119 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.124119 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.124119 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.124119 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.124119 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.601181 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13595.601181 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13595.601181 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13595.601181 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 4808 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 175 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 27.474286 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56203 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 56203 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 56203 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 56203 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 56203 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 56203 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1013449 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1013449 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1013449 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1013449 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1013449 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1013449 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11948814497 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11948814497 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11948814497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11948814497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11948814497 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11948814497 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117597 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.117597 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.117597 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11790.247459 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11790.247459 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.replacements 338368 # number of replacements
system.cpu.l2cache.tagsinuse 65364.962205 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2548619 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 403534 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.315748 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 4043215002 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 54020.981996 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 5337.307261 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6006.672948 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.824295 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.081441 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.091655 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.997390 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 998214 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 826620 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1824834 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 840489 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 840489 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 185505 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 185505 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 998214 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1012125 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2010339 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 998214 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1012125 # number of overall hits
system.cpu.l2cache.overall_hits::total 2010339 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 15114 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 273846 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 288960 # number of ReadReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 36 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 36 # number of UpgradeReq misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 115406 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 115406 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 15114 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 389252 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 404366 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 15114 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 389252 # number of overall misses
system.cpu.l2cache.overall_misses::total 404366 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 909377000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11791174000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 12700551000 # number of ReadReq miss cycles
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8601240000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8601240000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 909377000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 20392414000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 21301791000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 909377000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 20392414000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 21301791000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1013328 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1100466 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2113794 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 840489 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 840489 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 300911 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 300911 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1013328 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1401377 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2414705 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1013328 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1401377 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2414705 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014915 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248845 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.136702 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.580645 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.580645 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383522 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383522 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014915 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277764 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.167460 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014915 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277764 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.167460 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60167.857615 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43057.682055 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 43952.626661 # average ReadReq miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74530.267057 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74530.267057 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52679.480965 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52679.480965 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.writebacks::writebacks 75966 # number of writebacks
system.cpu.l2cache.writebacks::total 75966 # number of writebacks
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273846 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 288959 # number of ReadReq MSHR misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115406 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 115406 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15113 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 389252 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 404365 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15113 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 389252 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 404365 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 718571789 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8247220261 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8965792050 # number of ReadReq MSHR miss cycles
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7172240815 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7172240815 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 718571789 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15419461076 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16138032865 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 718571789 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15419461076 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16138032865 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333809500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333809500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882195500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882195500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216005000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216005000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248845 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136702 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.580645 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.580645 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383522 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383522 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.167459 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.167459 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47546.601535 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30116.270681 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31027.903786 # average ReadReq mshr miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62147.902319 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62147.902319 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.replacements 1400783 # number of replacements
system.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use
system.cpu.dcache.total_refs 11827578 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1401295 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 8.440463 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 7213661 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7213661 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4203894 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4203894 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 190181 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 190181 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 219613 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 219613 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 11417555 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 11417555 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 11417555 # number of overall hits
system.cpu.dcache.overall_hits::total 11417555 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1801125 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1801125 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1943246 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1943246 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3744371 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3744371 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3744371 # number of overall misses
system.cpu.dcache.overall_misses::total 3744371 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33805478000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 33805478000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 71113991647 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 71113991647 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303653500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 303653500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 104919469647 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 104919469647 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 104919469647 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 104919469647 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9014786 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9014786 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6147140 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6147140 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 212866 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 212866 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 219615 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 219615 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15161926 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15161926 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15161926 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15161926 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199797 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.199797 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316122 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.316122 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.106569 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.106569 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.246959 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.246959 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.246959 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.246959 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18769.090430 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18769.090430 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36595.465344 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36595.465344 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13385.651311 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13385.651311 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28020.586007 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28020.586007 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2640119 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 587 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 95652 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.601294 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 73.375000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 840489 # number of writebacks
system.cpu.dcache.writebacks::total 840489 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717559 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 717559 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642936 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1642936 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2360495 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2360495 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2360495 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2360495 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083566 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1083566 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300310 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 300310 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17562 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17562 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1383876 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1383876 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1383876 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1383876 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21170477000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21170477000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10817290277 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10817290277 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199800500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199800500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31987767277 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 31987767277 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31987767277 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 31987767277 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423886500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423886500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997350998 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997350998 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421237498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421237498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120199 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120199 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082503 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082503 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19537.782655 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19537.782655 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36020.413163 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36020.413163 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11376.864822 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.864822 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.inst.hwrei 210973 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74651 40.97% 40.97% # number of times we switched to this ipl
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105545 57.93% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182205 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73284 49.32% 49.32% # number of times we switched to this ipl from a different ipl
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73284 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148577 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1818516202000 98.07% 98.07% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 64252000 0.00% 98.07% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 558035000 0.03% 98.10% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 35210286000 1.90% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1854348775000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.ipl_used::31 0.694339 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.kern.syscall::total 326 # number of syscalls executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.callpal::swpipl 175092 91.23% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.callpal::total 191934 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches
system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1911
system.cpu.kern.mode_good::user 1741
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.kern.mode_good::idle 170
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.mode_switch_good::kernel 0.326778 # fraction of useful protection mode switches
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 29709775500 1.60% 1.60% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 2660669000 0.14% 1.75% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1821978322500 98.25% 100.00% # number of ticks spent at the given mode
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink