2010-01-30 05:29:17 +01:00
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/*
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2014-02-24 02:16:16 +01:00
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* Copyright (c) 2012-2013 ARM Limited
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MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2010-01-30 05:29:17 +01:00
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* Copyright (c) 2009 Advanced Micro Devices, Inc.
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2012-01-23 18:07:14 +01:00
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* Copyright (c) 2011 Mark D. Hill and David A. Wood
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2010-01-30 05:29:17 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2010-08-24 21:07:22 +02:00
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#include "cpu/testers/rubytest/RubyTester.hh"
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2012-01-11 20:48:48 +01:00
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#include "debug/Config.hh"
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2012-08-15 16:38:08 +02:00
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#include "debug/Drain.hh"
|
2011-04-15 19:44:32 +02:00
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#include "debug/Ruby.hh"
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2011-07-01 02:49:26 +02:00
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#include "mem/protocol/AccessPermission.hh"
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2010-01-30 05:29:17 +01:00
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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2010-03-23 02:43:53 +01:00
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#include "mem/ruby/system/RubyPort.hh"
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2014-11-06 12:42:21 +01:00
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#include "mem/simple_mem.hh"
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2014-03-20 14:03:09 +01:00
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#include "sim/full_system.hh"
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2012-03-30 15:42:36 +02:00
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#include "sim/system.hh"
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2009-07-07 00:49:47 +02:00
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2010-01-30 05:29:17 +01:00
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RubyPort::RubyPort(const Params *p)
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2015-07-10 23:05:23 +02:00
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: MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
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m_controller(NULL), m_mandatory_q_ptr(NULL),
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m_usingRubyTester(p->using_ruby_tester), system(p->system),
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2014-02-24 02:16:16 +01:00
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pioMasterPort(csprintf("%s.pio-master-port", name()), this),
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pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
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memMasterPort(csprintf("%s.mem-master-port", name()), this),
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memSlavePort(csprintf("%s-mem-slave-port", name()), this,
|
2015-07-10 23:05:23 +02:00
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p->ruby_system->getAccessBackingStore(), -1),
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2015-07-07 10:51:05 +02:00
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gotAddrRanges(p->port_master_connection_count)
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2010-01-30 05:29:17 +01:00
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{
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assert(m_version != -1);
|
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|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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// create the slave ports based on the number of connected ports
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for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
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2014-02-24 02:16:16 +01:00
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slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
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2015-07-10 23:05:23 +02:00
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|
|
i), this, p->ruby_system->getAccessBackingStore(), i));
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
}
|
2012-01-11 20:48:48 +01:00
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
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|
// create the master ports based on the number of connected ports
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for (size_t i = 0; i < p->port_master_connection_count; ++i) {
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2014-02-24 02:16:16 +01:00
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master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
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name(), i), this));
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
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}
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2010-01-30 05:29:17 +01:00
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}
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2010-03-23 02:43:53 +01:00
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void
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RubyPort::init()
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2010-01-30 05:29:19 +01:00
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{
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assert(m_controller != NULL);
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m_mandatory_q_ptr = m_controller->getMandatoryQueue();
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}
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2012-10-15 14:12:35 +02:00
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BaseMasterPort &
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RubyPort::getMasterPort(const std::string &if_name, PortID idx)
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2010-01-30 05:29:17 +01:00
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{
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2014-02-24 02:16:16 +01:00
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if (if_name == "mem_master_port") {
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return memMasterPort;
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}
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if (if_name == "pio_master_port") {
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return pioMasterPort;
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
}
|
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2012-02-13 12:43:09 +01:00
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// used by the x86 CPUs to connect the interrupt PIO and interrupt slave
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// port
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
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|
if (if_name != "master") {
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// pass it along to our super class
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return MemObject::getMasterPort(if_name, idx);
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|
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} else {
|
2012-10-15 14:12:35 +02:00
|
|
|
if (idx >= static_cast<PortID>(master_ports.size())) {
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
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|
panic("RubyPort::getMasterPort: unknown index %d\n", idx);
|
|
|
|
}
|
2012-02-13 12:43:09 +01:00
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
return *master_ports[idx];
|
2012-02-13 12:43:09 +01:00
|
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|
}
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
}
|
2012-02-13 12:43:09 +01:00
|
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|
2012-10-15 14:12:35 +02:00
|
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BaseSlavePort &
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RubyPort::getSlavePort(const std::string &if_name, PortID idx)
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
{
|
2014-02-24 02:16:16 +01:00
|
|
|
if (if_name == "mem_slave_port") {
|
|
|
|
return memSlavePort;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (if_name == "pio_slave_port")
|
|
|
|
return pioSlavePort;
|
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
// used by the CPUs to connect the caches to the interconnect, and
|
|
|
|
// for the x86 case also the interrupt master
|
|
|
|
if (if_name != "slave") {
|
|
|
|
// pass it along to our super class
|
|
|
|
return MemObject::getSlavePort(if_name, idx);
|
|
|
|
} else {
|
2012-10-15 14:12:35 +02:00
|
|
|
if (idx >= static_cast<PortID>(slave_ports.size())) {
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
panic("RubyPort::getSlavePort: unknown index %d\n", idx);
|
|
|
|
}
|
2010-03-23 02:43:53 +01:00
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
return *slave_ports[idx];
|
2010-03-23 02:43:53 +01:00
|
|
|
}
|
2010-01-30 05:29:17 +01:00
|
|
|
}
|
2010-01-30 05:29:19 +01:00
|
|
|
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
|
|
|
|
RubyPort *_port)
|
2015-03-02 10:00:35 +01:00
|
|
|
: QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
|
|
|
|
reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
|
2014-02-24 02:16:16 +01:00
|
|
|
{
|
|
|
|
DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
|
|
|
|
}
|
|
|
|
|
|
|
|
RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
|
|
|
|
RubyPort *_port)
|
|
|
|
: QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
|
|
|
|
{
|
|
|
|
DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
|
|
|
|
}
|
|
|
|
|
|
|
|
RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
|
2010-01-30 05:29:19 +01:00
|
|
|
RubyPort *_port)
|
2015-03-02 10:00:35 +01:00
|
|
|
: QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
|
|
|
|
reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2014-02-24 02:16:16 +01:00
|
|
|
DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name);
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port,
|
2014-11-06 12:42:21 +01:00
|
|
|
bool _access_backing_store, PortID id)
|
2014-02-24 02:16:16 +01:00
|
|
|
: QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
|
2015-07-10 23:05:23 +02:00
|
|
|
access_backing_store(_access_backing_store)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2014-02-24 02:16:16 +01:00
|
|
|
DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name);
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
2014-02-24 02:16:16 +01:00
|
|
|
bool
|
|
|
|
RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2015-07-10 23:05:23 +02:00
|
|
|
RubyPort *rp = static_cast<RubyPort *>(&owner);
|
2014-02-24 02:16:16 +01:00
|
|
|
DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
|
|
|
|
|
|
|
|
// send next cycle
|
2015-07-10 23:05:23 +02:00
|
|
|
rp->pioSlavePort.schedTimingResp(
|
|
|
|
pkt, curTick() + rp->m_ruby_system->clockPeriod());
|
2014-02-24 02:16:16 +01:00
|
|
|
return true;
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
2014-02-24 02:16:16 +01:00
|
|
|
bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2014-02-24 02:16:16 +01:00
|
|
|
// got a response from a device
|
|
|
|
assert(pkt->isResponse());
|
|
|
|
|
2014-02-24 02:16:16 +01:00
|
|
|
// First we must retrieve the request port from the sender State
|
|
|
|
RubyPort::SenderState *senderState =
|
|
|
|
safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
|
|
|
|
MemSlavePort *port = senderState->port;
|
|
|
|
assert(port != NULL);
|
|
|
|
delete senderState;
|
2010-03-23 02:43:53 +01:00
|
|
|
|
2015-01-22 11:01:24 +01:00
|
|
|
// In FS mode, ruby memory will receive pio responses from devices
|
|
|
|
// and it must forward these responses back to the particular CPU.
|
|
|
|
DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n",
|
|
|
|
pkt->getAddr(), port->name());
|
|
|
|
|
2014-02-24 02:16:16 +01:00
|
|
|
// attempt to send the response in the next cycle
|
2015-07-10 23:05:23 +02:00
|
|
|
RubyPort *rp = static_cast<RubyPort *>(&owner);
|
|
|
|
port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
|
2010-03-23 02:43:53 +01:00
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
|
|
|
|
|
|
|
|
for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
|
|
|
|
AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
|
|
|
|
for (auto it = l.begin(); it != l.end(); ++it) {
|
|
|
|
if (it->contains(pkt->getAddr())) {
|
2014-09-27 15:08:29 +02:00
|
|
|
// generally it is not safe to assume success here as
|
|
|
|
// the port could be blocked
|
|
|
|
bool M5_VAR_USED success =
|
|
|
|
ruby_port->master_ports[i]->sendTimingReq(pkt);
|
|
|
|
assert(success);
|
2014-02-24 02:16:16 +01:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
panic("Should never reach here!\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
|
|
|
|
{
|
|
|
|
DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
|
|
|
|
pkt->getAddr(), id);
|
|
|
|
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
|
2010-01-30 05:29:19 +01:00
|
|
|
|
2013-04-22 19:20:33 +02:00
|
|
|
if (pkt->memInhibitAsserted())
|
|
|
|
panic("RubyPort should never see an inhibited request\n");
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
// Check for pio requests and directly send them to the dedicated
|
|
|
|
// pio port.
|
|
|
|
if (!isPhysMemAddress(pkt->getAddr())) {
|
2014-02-24 02:16:16 +01:00
|
|
|
assert(ruby_port->memMasterPort.isConnected());
|
|
|
|
DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n",
|
2010-01-30 05:29:33 +01:00
|
|
|
pkt->getAddr());
|
2010-01-30 05:29:19 +01:00
|
|
|
|
2014-02-24 02:16:16 +01:00
|
|
|
// Save the port in the sender state object to be used later to
|
|
|
|
// route the response
|
|
|
|
pkt->pushSenderState(new SenderState(this));
|
|
|
|
|
2012-08-22 17:39:56 +02:00
|
|
|
// send next cycle
|
2015-07-10 23:05:23 +02:00
|
|
|
RubySystem *rs = ruby_port->m_ruby_system;
|
2014-02-24 02:16:16 +01:00
|
|
|
ruby_port->memMasterPort.schedTimingReq(pkt,
|
2015-07-10 23:05:23 +02:00
|
|
|
curTick() + rs->clockPeriod());
|
2012-08-22 17:39:56 +02:00
|
|
|
return true;
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
2015-08-14 19:04:51 +02:00
|
|
|
assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
|
2011-11-15 00:44:35 +01:00
|
|
|
RubySystem::getBlockSizeBytes());
|
2011-02-07 07:14:18 +01:00
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
// Submit the ruby request
|
2011-11-15 00:44:35 +01:00
|
|
|
RequestStatus requestStatus = ruby_port->makeRequest(pkt);
|
2010-03-22 05:22:21 +01:00
|
|
|
|
2010-08-20 20:46:12 +02:00
|
|
|
// If the request successfully issued then we should return true.
|
2014-02-24 02:16:16 +01:00
|
|
|
// Otherwise, we need to tell the port to retry at a later point
|
|
|
|
// and return false.
|
2010-08-20 20:46:12 +02:00
|
|
|
if (requestStatus == RequestStatus_Issued) {
|
2015-01-22 11:01:24 +01:00
|
|
|
// Save the port in the sender state object to be used later to
|
|
|
|
// route the response
|
|
|
|
pkt->pushSenderState(new SenderState(this));
|
|
|
|
|
2014-02-24 02:16:16 +01:00
|
|
|
DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(),
|
|
|
|
pkt->getAddr());
|
2010-01-30 05:29:33 +01:00
|
|
|
return true;
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
2010-03-22 05:22:21 +01:00
|
|
|
|
2011-02-07 07:14:18 +01:00
|
|
|
//
|
2015-07-10 23:05:23 +02:00
|
|
|
// Unless one is using the ruby tester, record the stalled M5 port for
|
2011-02-07 07:14:18 +01:00
|
|
|
// later retry when the sequencer becomes free.
|
|
|
|
//
|
|
|
|
if (!ruby_port->m_usingRubyTester) {
|
|
|
|
ruby_port->addToRetryList(this);
|
|
|
|
}
|
|
|
|
|
2014-02-24 02:16:16 +01:00
|
|
|
DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n",
|
2010-03-23 02:43:53 +01:00
|
|
|
pkt->getAddr(), RequestStatus_to_string(requestStatus));
|
|
|
|
|
2010-01-30 05:29:33 +01:00
|
|
|
return false;
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
2011-07-01 02:49:26 +02:00
|
|
|
void
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
|
2011-07-01 02:49:26 +02:00
|
|
|
{
|
2014-02-24 02:16:16 +01:00
|
|
|
DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
|
2011-07-01 02:49:26 +02:00
|
|
|
|
2015-07-10 23:05:23 +02:00
|
|
|
RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner);
|
|
|
|
RubySystem *rs = rp->m_ruby_system;
|
|
|
|
|
2011-07-01 02:49:26 +02:00
|
|
|
// Check for pio requests and directly send them to the dedicated
|
|
|
|
// pio port.
|
|
|
|
if (!isPhysMemAddress(pkt->getAddr())) {
|
2015-07-10 23:05:23 +02:00
|
|
|
assert(rp->memMasterPort.isConnected());
|
2014-02-24 02:16:16 +01:00
|
|
|
DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
|
|
|
|
panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n");
|
2011-07-01 02:49:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
assert(pkt->getAddr() + pkt->getSize() <=
|
2015-08-14 19:04:51 +02:00
|
|
|
makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
|
2011-07-01 02:49:26 +02:00
|
|
|
|
2014-11-06 12:42:21 +01:00
|
|
|
if (access_backing_store) {
|
2011-07-01 02:49:26 +02:00
|
|
|
// The attached physmem contains the official version of data.
|
|
|
|
// The following command performs the real functional access.
|
|
|
|
// This line should be removed once Ruby supplies the official version
|
|
|
|
// of data.
|
2015-07-10 23:05:23 +02:00
|
|
|
rs->getPhysMem()->functionalAccess(pkt);
|
2015-02-26 16:58:26 +01:00
|
|
|
} else {
|
|
|
|
bool accessSucceeded = false;
|
|
|
|
bool needsResponse = pkt->needsResponse();
|
|
|
|
|
|
|
|
// Do the functional access on ruby memory
|
|
|
|
if (pkt->isRead()) {
|
2015-07-10 23:05:23 +02:00
|
|
|
accessSucceeded = rs->functionalRead(pkt);
|
2015-02-26 16:58:26 +01:00
|
|
|
} else if (pkt->isWrite()) {
|
2015-07-10 23:05:23 +02:00
|
|
|
accessSucceeded = rs->functionalWrite(pkt);
|
2015-02-26 16:58:26 +01:00
|
|
|
} else {
|
|
|
|
panic("Unsupported functional command %s\n", pkt->cmdString());
|
|
|
|
}
|
2011-07-01 02:49:26 +02:00
|
|
|
|
2015-02-26 16:58:26 +01:00
|
|
|
// Unless the requester explicitly said otherwise, generate an error if
|
|
|
|
// the functional request failed
|
|
|
|
if (!accessSucceeded && !pkt->suppressFuncError()) {
|
|
|
|
fatal("Ruby functional %s failed for address %#x\n",
|
|
|
|
pkt->isWrite() ? "write" : "read", pkt->getAddr());
|
|
|
|
}
|
2014-11-06 12:42:21 +01:00
|
|
|
|
2015-02-26 16:58:26 +01:00
|
|
|
// turn packet around to go back to requester if response expected
|
|
|
|
if (needsResponse) {
|
|
|
|
pkt->setFunctionalResponseStatus(accessSucceeded);
|
|
|
|
}
|
|
|
|
|
|
|
|
DPRINTF(RubyPort, "Functional access %s!\n",
|
|
|
|
accessSucceeded ? "successful":"failed");
|
|
|
|
}
|
2011-07-01 02:49:26 +02:00
|
|
|
}
|
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
void
|
2010-01-30 05:29:33 +01:00
|
|
|
RubyPort::ruby_hit_callback(PacketPtr pkt)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2014-02-24 02:16:16 +01:00
|
|
|
DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
|
|
|
|
pkt->getAddr());
|
|
|
|
|
|
|
|
// The packet was destined for memory and has not yet been turned
|
|
|
|
// into a response
|
|
|
|
assert(system->isMemAddr(pkt->getAddr()));
|
|
|
|
assert(pkt->isRequest());
|
2010-03-23 02:43:53 +01:00
|
|
|
|
2015-01-22 11:01:24 +01:00
|
|
|
// First we must retrieve the request port from the sender State
|
|
|
|
RubyPort::SenderState *senderState =
|
|
|
|
safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
|
|
|
|
MemSlavePort *port = senderState->port;
|
|
|
|
assert(port != NULL);
|
|
|
|
delete senderState;
|
2010-01-30 05:29:19 +01:00
|
|
|
|
2015-01-22 11:01:24 +01:00
|
|
|
port->hitCallback(pkt);
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
|
|
//
|
2014-02-24 02:16:16 +01:00
|
|
|
// If we had to stall the MemSlavePorts, wake them up because the sequencer
|
2011-02-07 07:14:18 +01:00
|
|
|
// likely has free resources now.
|
|
|
|
//
|
2014-02-24 02:16:16 +01:00
|
|
|
if (!retryList.empty()) {
|
2011-03-19 22:17:48 +01:00
|
|
|
//
|
|
|
|
// Record the current list of ports to retry on a temporary list before
|
2015-07-10 23:05:23 +02:00
|
|
|
// calling sendRetry on those ports. sendRetry will cause an
|
2011-03-19 22:17:48 +01:00
|
|
|
// immediate retry, which may result in the ports being put back on the
|
|
|
|
// list. Therefore we want to clear the retryList before calling
|
|
|
|
// sendRetry.
|
|
|
|
//
|
2014-02-24 02:16:16 +01:00
|
|
|
std::vector<MemSlavePort *> curRetryList(retryList);
|
2011-03-19 22:17:48 +01:00
|
|
|
|
|
|
|
retryList.clear();
|
2014-02-24 02:16:16 +01:00
|
|
|
|
|
|
|
for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort,
|
2011-02-07 07:14:18 +01:00
|
|
|
"Sequencer may now be free. SendRetry to port %s\n",
|
|
|
|
(*i)->name());
|
2015-03-02 10:00:35 +01:00
|
|
|
(*i)->sendRetryReq();
|
2011-02-07 07:14:18 +01:00
|
|
|
}
|
|
|
|
}
|
2012-01-11 20:48:48 +01:00
|
|
|
|
|
|
|
testDrainComplete();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
RubyPort::testDrainComplete()
|
|
|
|
{
|
|
|
|
//If we weren't able to drain before, we might be able to now.
|
2015-07-07 10:51:05 +02:00
|
|
|
if (drainState() == DrainState::Draining) {
|
2012-09-23 20:57:08 +02:00
|
|
|
unsigned int drainCount = outstandingCount();
|
2012-08-15 16:38:08 +02:00
|
|
|
DPRINTF(Drain, "Drain count: %u\n", drainCount);
|
2012-01-11 20:48:48 +01:00
|
|
|
if (drainCount == 0) {
|
2012-11-02 17:32:01 +01:00
|
|
|
DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
|
2015-07-07 10:51:05 +02:00
|
|
|
signalDrainDone();
|
2012-01-11 20:48:48 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-07-07 10:51:05 +02:00
|
|
|
DrainState
|
|
|
|
RubyPort::drain()
|
2012-01-11 20:48:48 +01:00
|
|
|
{
|
|
|
|
if (isDeadlockEventScheduled()) {
|
|
|
|
descheduleDeadlockEvent();
|
|
|
|
}
|
|
|
|
|
2012-09-23 20:57:08 +02:00
|
|
|
//
|
|
|
|
// If the RubyPort is not empty, then it needs to clear all outstanding
|
2015-07-07 10:51:05 +02:00
|
|
|
// requests before it should call signalDrainDone()
|
2012-09-23 20:57:08 +02:00
|
|
|
//
|
|
|
|
DPRINTF(Config, "outstanding count %d\n", outstandingCount());
|
2015-07-07 10:51:05 +02:00
|
|
|
if (outstandingCount() > 0) {
|
2012-08-15 16:38:08 +02:00
|
|
|
DPRINTF(Drain, "RubyPort not drained\n");
|
2015-07-07 10:51:05 +02:00
|
|
|
return DrainState::Draining;
|
|
|
|
} else {
|
|
|
|
return DrainState::Drained;
|
2012-01-11 20:48:48 +01:00
|
|
|
}
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
|
|
|
bool needsResponse = pkt->needsResponse();
|
|
|
|
|
2015-07-10 23:05:23 +02:00
|
|
|
// Unless specified at configuraiton, all responses except failed SC
|
2011-03-28 17:49:45 +02:00
|
|
|
// and Flush operations access M5 physical memory.
|
2014-11-06 12:42:21 +01:00
|
|
|
bool accessPhysMem = access_backing_store;
|
2010-08-20 20:46:12 +02:00
|
|
|
|
|
|
|
if (pkt->isLLSC()) {
|
|
|
|
if (pkt->isWrite()) {
|
|
|
|
if (pkt->req->getExtraData() != 0) {
|
|
|
|
//
|
|
|
|
// Successful SC packets convert to normal writes
|
|
|
|
//
|
|
|
|
pkt->convertScToWrite();
|
|
|
|
} else {
|
|
|
|
//
|
|
|
|
// Failed SC packets don't access physical memory and thus
|
|
|
|
// the RubyPort itself must convert it to a response.
|
|
|
|
//
|
|
|
|
accessPhysMem = false;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
//
|
|
|
|
// All LL packets convert to normal loads so that M5 PhysMem does
|
|
|
|
// not lock the blocks.
|
|
|
|
//
|
|
|
|
pkt->convertLlToRead();
|
|
|
|
}
|
|
|
|
}
|
2011-03-28 17:49:45 +02:00
|
|
|
|
|
|
|
// Flush requests don't access physical memory
|
|
|
|
if (pkt->isFlush()) {
|
|
|
|
accessPhysMem = false;
|
|
|
|
}
|
|
|
|
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
|
2010-01-30 05:29:19 +01:00
|
|
|
|
2015-07-10 23:05:23 +02:00
|
|
|
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
|
|
|
|
RubySystem *rs = ruby_port->m_ruby_system;
|
2010-08-20 20:46:12 +02:00
|
|
|
if (accessPhysMem) {
|
2015-07-10 23:05:23 +02:00
|
|
|
rs->getPhysMem()->access(pkt);
|
2011-03-28 17:49:45 +02:00
|
|
|
} else if (needsResponse) {
|
2011-02-07 07:14:19 +01:00
|
|
|
pkt->makeResponse();
|
2010-08-20 20:46:12 +02:00
|
|
|
}
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
// turn packet around to go back to requester if response expected
|
|
|
|
if (needsResponse) {
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort, "Sending packet back over port\n");
|
2015-07-20 16:15:18 +02:00
|
|
|
// Send a response in the same cycle. There is no need to delay the
|
|
|
|
// response because the response latency is already incurred in the
|
|
|
|
// Ruby protocol.
|
|
|
|
schedTimingResp(pkt, curTick());
|
2010-01-30 05:29:19 +01:00
|
|
|
} else {
|
|
|
|
delete pkt;
|
|
|
|
}
|
2014-11-06 12:42:21 +01:00
|
|
|
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort, "Hit callback done!\n");
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
AddrRangeList
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort::PioSlavePort::getAddrRanges() const
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
{
|
|
|
|
// at the moment the assumption is that the master does not care
|
|
|
|
AddrRangeList ranges;
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
|
|
|
|
|
|
|
|
for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
|
|
|
|
ranges.splice(ranges.begin(),
|
|
|
|
ruby_port->master_ports[i]->getAddrRanges());
|
|
|
|
}
|
2014-10-16 11:49:59 +02:00
|
|
|
for (const auto M5_VAR_USED &r : ranges)
|
|
|
|
DPRINTF(RubyPort, "%s\n", r.to_string());
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
return ranges;
|
|
|
|
}
|
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
bool
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2014-02-24 02:16:16 +01:00
|
|
|
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
|
2012-04-06 19:46:31 +02:00
|
|
|
return ruby_port->system->isMemAddr(addr);
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
2011-02-07 07:14:18 +01:00
|
|
|
|
2012-01-23 18:07:14 +01:00
|
|
|
void
|
2015-08-14 19:04:51 +02:00
|
|
|
RubyPort::ruby_eviction_callback(Addr address)
|
2012-01-23 18:07:14 +01:00
|
|
|
{
|
|
|
|
DPRINTF(RubyPort, "Sending invalidations.\n");
|
2015-09-29 16:28:25 +02:00
|
|
|
// Allocate the invalidate request and packet on the stack, as it is
|
|
|
|
// assumed they will not be modified or deleted by receivers.
|
2013-04-09 23:25:30 +02:00
|
|
|
// TODO: should this really be using funcMasterId?
|
2015-09-29 16:28:25 +02:00
|
|
|
Request request(address, RubySystem::getBlockSizeBytes(), 0,
|
|
|
|
Request::funcMasterId);
|
2013-04-09 23:25:30 +02:00
|
|
|
// Use a single packet to signal all snooping ports of the invalidation.
|
|
|
|
// This assumes that snooping ports do NOT modify the packet/request
|
2015-09-29 16:28:25 +02:00
|
|
|
Packet pkt(&request, MemCmd::InvalidateReq);
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
|
2012-07-09 18:35:32 +02:00
|
|
|
// check if the connected master port is snooping
|
|
|
|
if ((*p)->isSnooping()) {
|
MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
|
|
|
// send as a snoop request
|
2013-04-09 23:25:30 +02:00
|
|
|
(*p)->sendTimingSnoopReq(&pkt);
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
}
|
2012-01-23 18:07:14 +01:00
|
|
|
}
|
|
|
|
}
|
2014-02-24 02:16:16 +01:00
|
|
|
|
|
|
|
void
|
|
|
|
RubyPort::PioMasterPort::recvRangeChange()
|
|
|
|
{
|
|
|
|
RubyPort &r = static_cast<RubyPort &>(owner);
|
|
|
|
r.gotAddrRanges--;
|
2014-03-20 14:03:09 +01:00
|
|
|
if (r.gotAddrRanges == 0 && FullSystem) {
|
2014-02-24 02:16:16 +01:00
|
|
|
r.pioSlavePort.sendRangeChange();
|
|
|
|
}
|
|
|
|
}
|