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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

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ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
---------- Begin Simulation Statistics ----------
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
sim_seconds 2.523500 # Number of seconds simulated
sim_ticks 2523500318000 # Number of ticks simulated
final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
host_inst_rate 66325 # Simulator instruction rate (inst/s)
host_op_rate 85314 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2762063576 # Simulator tick rate (ticks/s)
host_mem_usage 400896 # Number of bytes of host memory used
host_seconds 913.63 # Real time elapsed on the host
sim_insts 60596849 # Number of instructions simulated
sim_ops 77944928 # Number of ops (including micro ops) simulated
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory
system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15096860 # Total number of read requests seen
system.physmem.writeReqs 813144 # Total number of write requests seen
system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 966199040 # Total number of bytes read from memory
system.physmem.bytesWritten 52041216 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis
stats: Update the stats to reflect the 1GHz default system clock This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25 19:15:59 +02:00
system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis
stats: Update the stats to reflect the 1GHz default system clock This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25 19:15:59 +02:00
system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis
stats: Update the stats to reflect the 1GHz default system clock This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25 19:15:59 +02:00
system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry
system.physmem.totGap 2523499110500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.readPktSize::6 154616 # Categorize read packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.writePktSize::2 1907897 # categorize write packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.writePktSize::6 59126 # categorize write packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see
stats: Update the stats to reflect the 1GHz default system clock This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25 19:15:59 +02:00
system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
stats: Update the stats to reflect the 1GHz default system clock This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25 19:15:59 +02:00
system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests
system.physmem.totBusLat 60386104000 # Total cycles spent in databus access
system.physmem.totBankLat 210282128000 # Total cycles spent in bank access
system.physmem.avgQLat 3116.78 # Average queueing delay per request
system.physmem.avgBankLat 13929.17 # Average bank access latency per request
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgBusLat 4000.00 # Average bus latency per request
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.avgMemAccLat 21045.95 # Average memory access latency
system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.52 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.13 # Average read queue length over time
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.avgWrQLen 11.37 # Average write queue length over time
system.physmem.readRowHits 15049962 # Number of row buffer hits during reads
system.physmem.writeRowHits 784769 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes
system.physmem.avgGap 158610.84 # Average gap between requests
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.read_hits 51279526 # DTB read hits
system.cpu.dtb.read_misses 73667 # DTB read misses
system.cpu.dtb.write_hits 11753863 # DTB write hits
system.cpu.dtb.write_misses 17234 # DTB write misses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.flush_entries 4224 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 51353193 # DTB read accesses
system.cpu.dtb.write_accesses 11771097 # DTB write accesses
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.hits 63033389 # DTB hits
system.cpu.dtb.misses 90901 # DTB misses
system.cpu.dtb.accesses 63124290 # DTB accesses
system.cpu.itb.inst_hits 11603865 # ITB inst hits
system.cpu.itb.inst_misses 11359 # ITB inst misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.itb.flush_entries 2573 # Number of entries that have been flushed from TLB
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.itb.inst_accesses 11615224 # ITB inst accesses
system.cpu.itb.hits 11603865 # DTB hits
system.cpu.itb.misses 11359 # DTB misses
system.cpu.itb.accesses 11615224 # DTB accesses
system.cpu.numCycles 470951029 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued
system.cpu.iq.rate 0.261997 # Inst issue rate
system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.exec_nop 220747 # number of nop insts executed
system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed
system.cpu.iew.exec_branches 11527542 # Number of branches executed
system.cpu.iew.exec_stores 12265452 # Number of stores executed
system.cpu.iew.exec_rate 0.257499 # Inst execution rate
system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back
system.cpu.iew.wb_producers 47162688 # num instructions producing a value
system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle
system.cpu.commit.committedInsts 60747230 # Number of instructions committed
system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.refs 27514399 # Number of memory references committed
system.cpu.commit.loads 15715935 # Number of loads committed
system.cpu.commit.membars 413101 # Number of memory barriers committed
system.cpu.commit.branches 10023041 # Number of branches committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.int_insts 69133795 # Number of committed integer instructions.
system.cpu.commit.function_calls 995976 # Number of function calls committed.
system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.rob.rob_reads 239806361 # The number of ROB reads
system.cpu.rob.rob_writes 197293644 # The number of ROB writes
system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 60596849 # Number of Instructions Simulated
system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated
system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads
system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 549353817 # number of integer regfile reads
system.cpu.int_regfile_writes 87979071 # number of integer regfile writes
system.cpu.fp_regfile_reads 8318 # number of floating regfile reads
system.cpu.fp_regfile_writes 2932 # number of floating regfile writes
system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads
system.cpu.misc_regfile_writes 912865 # number of misc regfile writes
system.cpu.icache.replacements 980837 # number of replacements
system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use
system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits
system.cpu.icache.overall_hits::total 10539450 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses
system.cpu.icache.overall_misses::total 1060605 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.091431 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.091431 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13163.622169 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79214 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 79214 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 79214 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 79214 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 79214 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 79214 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981391 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 981391 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 981391 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 981391 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 981391 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 981391 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11354795991 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11354795991 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11354795991 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084602 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.084602 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.084602 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11570.104057 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11570.104057 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.replacements 64388 # number of replacements
system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 129780 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 14.728779 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2488431429000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 36915.014302 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 29.696477 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 8183.272105 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6245.619403 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.563278 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000453 # Average percentage of cache occupancy
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.occ_percent::cpu.inst 0.124867 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.095301 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.783899 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79304 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10595 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 967765 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 387173 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1444837 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 607749 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 607749 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 112887 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 112887 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 79304 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 10595 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 967765 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 500060 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1557724 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 79304 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 10595 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 967765 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 500060 # number of overall hits
system.cpu.l2cache.overall_hits::total 1557724 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 43 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 10735 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 23152 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 133176 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133176 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 43 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 12372 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143911 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 156328 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 43 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 12372 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143911 # number of overall misses
system.cpu.l2cache.overall_misses::total 156328 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2913500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 660133000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590903498 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1254067998 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 477000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 477000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6777740498 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6777740498 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2913500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 660133000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7368643996 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 8031808496 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2913500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 660133000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7368643996 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 8031808496 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 79347 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10597 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 980137 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 397908 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1467989 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 607749 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 607749 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246063 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 246063 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 79347 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 10597 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 980137 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 643971 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1714052 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 79347 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 10597 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 980137 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 643971 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1714052 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000542 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012623 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.015771 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985478 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985478 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541227 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541227 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000542 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012623 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.223474 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.091204 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000542 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012623 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.223474 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.091204 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 67755.813953 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53357.015842 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55044.573638 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54166.724171 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.468129 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.468129 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50893.107602 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50893.107602 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51377.926513 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 67755.813953 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53357.015842 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51202.785027 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51377.926513 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.writebacks::writebacks 59126 # number of writebacks
system.cpu.l2cache.writebacks::total 59126 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 43 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12360 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10675 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 23080 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2918 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 43 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12360 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143851 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 43 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12360 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143851 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 156256 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2368082 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93002 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503399135 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 452451368 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 958311587 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29209900 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29209900 # number of UpgradeReq MSHR miss cycles
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5125972608 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5125972608 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2368082 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503399135 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578423976 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6084284195 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2368082 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503399135 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578423976 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6084284195 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963877530 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166968222685 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18087556027 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18087556027 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185051433557 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185055778712 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.replacements 643459 # number of replacements
system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits
system.cpu.dcache.overall_hits::total 21094791 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses
system.cpu.dcache.overall_misses::total 3692032 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks
system.cpu.dcache.writebacks::total 607749 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_refs nan # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink