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checker
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Faults generated at fetch are passed to the backend by creating a dummy nop instruction and giving it the fault. This unifies front end faults and normal instruction faults.
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2006-05-17 14:25:10 -04:00 |
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memtest
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Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.
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2006-03-04 15:18:40 -05:00 |
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o3
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Rename function to be more expressive.
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2006-05-19 15:45:06 -04:00 |
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ozone
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Fixes for regression build errors.
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2006-05-19 14:27:46 -04:00 |
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simple
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Fixes for the sampler.
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2006-05-03 15:54:36 -04:00 |
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trace
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Made Addr a global type
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2006-02-21 03:38:21 -05:00 |
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activity.cc
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Move activity tracking code into its own class. Now the CPU no longer has to keep track of the activity tracking internals; it just calls advance() on the class and uses it to tell if it should deschedule itself.
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2006-05-19 15:37:52 -04:00 |
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activity.hh
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Move activity tracking code into its own class. Now the CPU no longer has to keep track of the activity tracking internals; it just calls advance() on the class and uses it to tell if it should deschedule itself.
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2006-05-19 15:37:52 -04:00 |
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base.cc
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Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU.
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2006-05-16 13:59:29 -04:00 |
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base.hh
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Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU.
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2006-05-16 13:59:29 -04:00 |
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base_dyn_inst.cc
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Separate out result being ready and the instruction being complete.
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2006-05-11 14:12:34 -04:00 |
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base_dyn_inst.hh
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Fixes for ozone CPU to successfully boot and run linux.
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2006-05-11 19:18:36 -04:00 |
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cpu_exec_context.cc
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Fixes for regression build errors.
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2006-05-19 14:27:46 -04:00 |
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cpu_exec_context.hh
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Sampling fixes related to the quiesce event.
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2006-05-16 13:51:18 -04:00 |
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cpu_models.py
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Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU.
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2006-05-16 13:59:29 -04:00 |
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exec_context.hh
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Sampling fixes related to the quiesce event.
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2006-05-16 13:51:18 -04:00 |
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exetrace.cc
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Allow the switching on and off of PC symbols for tracing.
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2006-04-24 16:56:24 -04:00 |
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exetrace.hh
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Allow the switching on and off of PC symbols for tracing.
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2006-04-24 16:56:24 -04:00 |
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inst_seq.hh
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Include option for disabling PC symbols.
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2006-04-24 17:11:31 -04:00 |
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intr_control.cc
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Updates for the quiesceEvent that was added to the XC.
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2006-03-07 19:59:12 -05:00 |
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intr_control.hh
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Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.
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2006-03-04 15:18:40 -05:00 |
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pc_event.cc
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Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.
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2006-03-04 15:18:40 -05:00 |
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pc_event.hh
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Made Addr a global type
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2006-02-21 03:38:21 -05:00 |
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profile.cc
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Updates for the quiesceEvent that was added to the XC.
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2006-03-07 19:59:12 -05:00 |
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profile.hh
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Updates for the quiesceEvent that was added to the XC.
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2006-03-07 19:59:12 -05:00 |
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quiesce_event.cc
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Move quiesce event to its own class.
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2006-04-22 18:11:54 -04:00 |
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quiesce_event.hh
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Move quiesce event to its own class.
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2006-04-22 18:11:54 -04:00 |
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SConscript
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Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU.
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2006-05-16 13:59:29 -04:00 |
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smt.hh
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Many files:
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2005-06-05 05:16:00 -04:00 |
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static_inst.cc
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Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
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2006-02-19 02:34:37 -05:00 |
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static_inst.hh
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Add some flags for the upcoming checker.
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2006-05-16 13:48:05 -04:00 |
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thread_state.hh
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Updates for O3 model.
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2006-04-22 18:26:48 -04:00 |
