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alpha
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X86: Fix argument register indexing.
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2007-07-26 22:13:14 -07:00 |
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mips
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X86: Fix argument register indexing.
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2007-07-26 22:13:14 -07:00 |
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sparc
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X86: Fix argument register indexing.
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2007-07-26 22:13:14 -07:00 |
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2bit_local_pred.cc
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Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
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2006-06-04 16:07:54 -04:00 |
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2bit_local_pred.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
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base_dyn_inst.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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bpred_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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bpred_unit.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
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bpred_unit_impl.hh
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Make sure the value of PC is actually updated now that the instruction target isn't set explicitly.
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2006-12-28 14:29:17 -05:00 |
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btb.cc
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
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btb.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
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checker_builder.cc
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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comm.hh
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Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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2007-04-14 17:13:18 +00:00 |
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commit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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commit.hh
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Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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2007-04-14 17:13:18 +00:00 |
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commit_impl.hh
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Event descriptions should not end in "event"
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2007-06-30 17:45:58 -07:00 |
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cpu.cc
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Merge python and x86 changes with cache branch
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2007-07-26 23:15:49 -07:00 |
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cpu.hh
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Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-06-21 20:35:25 +00:00 |
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cpu_policy.hh
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Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
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2006-06-04 16:07:54 -04:00 |
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decode.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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decode.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
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decode_impl.hh
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Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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2007-04-14 17:13:18 +00:00 |
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dep_graph.hh
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Miscellaneous minor fixes.
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2006-06-16 17:15:18 -04:00 |
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dyn_inst.hh
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Added an x86 dyninst
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2007-03-05 14:55:45 +00:00 |
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fetch.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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fetch.hh
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Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-06-19 18:54:40 -07:00 |
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fetch_impl.hh
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Get rid of Packet result field. Error responses are
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2007-06-30 10:16:18 -07:00 |
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free_list.cc
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
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free_list.hh
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Make the floating point zero register special handling only apply for ALPHA.
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2007-04-22 17:50:43 +00:00 |
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fu_pool.cc
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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fu_pool.hh
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Update copyright.
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2006-06-07 16:02:55 -04:00 |
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FuncUnitConfig.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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FUPool.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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iew.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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iew.hh
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Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
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2007-04-13 13:59:31 +00:00 |
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iew_impl.hh
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Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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2007-04-14 17:13:18 +00:00 |
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inst_queue.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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inst_queue.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
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inst_queue_impl.hh
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Merge python and x86 changes with cache branch
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2007-07-26 23:15:49 -07:00 |
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isa_specific.hh
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Initial changes to get O3 working with SPARC
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2006-11-24 22:06:33 -05:00 |
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lsq.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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lsq.hh
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Change getDeviceAddressRanges to use bool for snoop arg.
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2007-05-21 23:36:09 -07:00 |
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lsq_impl.hh
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Fix up a bunch of multilevel coherence issues.
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2007-07-15 20:11:06 -07:00 |
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lsq_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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lsq_unit.hh
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Make CPU models use new LoadLockedReq/StoreCondReq commands.
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2007-06-30 20:35:42 -07:00 |
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lsq_unit_impl.hh
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Fix WriteReq/StoreCondReq setting in O3.
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2007-07-23 08:18:51 -07:00 |
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mem_dep_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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mem_dep_unit.hh
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Initialize mem dep unit properly.
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2006-11-07 13:53:06 -05:00 |
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mem_dep_unit_impl.hh
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Handle status bits a little better, as well as non-speculative instructions.
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2007-03-23 11:40:53 -04:00 |
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O3Checker.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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O3CPU.py
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Make sure all parameters have default values if they're
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2007-06-20 08:14:11 -07:00 |
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params.hh
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Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
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2006-10-31 14:33:56 -05:00 |
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ras.cc
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
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ras.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
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regfile.hh
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Make the floating point zero register special handling only apply for ALPHA.
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2007-04-22 17:50:43 +00:00 |
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rename.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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rename.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
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rename_impl.hh
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Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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2007-04-14 17:13:18 +00:00 |
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rename_map.cc
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Make the floating point zero register special handling only apply for ALPHA.
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2007-04-22 17:50:43 +00:00 |
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rename_map.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
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rob.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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rob.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
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rob_impl.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
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sat_counter.cc
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
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sat_counter.hh
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
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SConscript
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Fix cut-n-pasto to make the path correct
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2007-05-30 17:19:20 -07:00 |
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SConsopts
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Rework the way SCons recurses into subdirectories, making it
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2007-03-10 23:00:54 -08:00 |
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scoreboard.cc
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Make the floating point zero register special handling only apply for ALPHA.
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2007-04-22 17:50:43 +00:00 |
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scoreboard.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
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store_set.cc
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Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses.
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2006-06-05 18:14:39 -04:00 |
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store_set.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
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thread_context.hh
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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thread_context_impl.hh
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fix segfault when peer owner attempts to use functional port
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2007-03-13 17:34:52 -04:00 |
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thread_state.hh
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Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
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2006-10-31 14:33:56 -05:00 |
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tournament_pred.cc
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Merge ktlim@zamp:./local/clean/o3-merge/m5
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2006-09-30 23:43:23 -04:00 |
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tournament_pred.hh
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Merge ktlim@zamp:./local/clean/o3-merge/m5
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2006-09-30 23:43:23 -04:00 |
