298 lines
9.4 KiB
C++
298 lines
9.4 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Gabe Black
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*/
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#ifndef __CPU_O3_REGFILE_HH__
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#define __CPU_O3_REGFILE_HH__
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#include "arch/isa_traits.hh"
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#include "arch/types.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/o3/comm.hh"
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#if FULL_SYSTEM
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#include "arch/kernel_stats.hh"
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#endif
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#include <vector>
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/**
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* Simple physical register file class.
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* Right now this is specific to Alpha until we decide if/how to make things
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* generic enough to support other ISAs.
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*/
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template <class Impl>
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class PhysRegFile
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{
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protected:
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::MiscRegFile MiscRegFile;
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typedef TheISA::MiscReg MiscReg;
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typedef union {
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FloatReg d;
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FloatRegBits q;
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} PhysFloatReg;
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// Note that most of the definitions of the IntReg, FloatReg, etc. exist
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// within the Impl/ISA class and not within this PhysRegFile class.
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// Will make these registers public for now, but they probably should
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// be private eventually with some accessor functions.
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public:
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typedef typename Impl::O3CPU O3CPU;
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/**
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* Constructs a physical register file with the specified amount of
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* integer and floating point registers.
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*/
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PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
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unsigned _numPhysicalFloatRegs);
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//Everything below should be pretty well identical to the normal
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//register file that exists within AlphaISA class.
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//The duplication is unfortunate but it's better than having
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//different ways to access certain registers.
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/** Reads an integer register. */
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uint64_t readIntReg(PhysRegIndex reg_idx)
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{
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assert(reg_idx < numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to int register %i, has data "
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"%#x\n", int(reg_idx), intRegFile[reg_idx]);
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return intRegFile[reg_idx];
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}
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FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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FloatReg floatReg = floatRegFile[reg_idx].d;
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DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
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"data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
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return floatReg;
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}
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/** Reads a floating point register (double precision). */
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FloatReg readFloatReg(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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FloatReg floatReg = floatRegFile[reg_idx].d;
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DPRINTF(IEW, "RegFile: Access to float register %i, has "
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"data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
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return floatReg;
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}
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/** Reads a floating point register as an integer. */
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FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
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DPRINTF(IEW, "RegFile: Access to float register %i as int, "
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"has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
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return floatRegBits;
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}
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FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
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DPRINTF(IEW, "RegFile: Access to float register %i as int, "
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"has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
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return floatRegBits;
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}
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/** Sets an integer register to the given value. */
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void setIntReg(PhysRegIndex reg_idx, uint64_t val)
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{
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assert(reg_idx < numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
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int(reg_idx), val);
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if (reg_idx != TheISA::ZeroReg)
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intRegFile[reg_idx] = val;
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}
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/** Sets a single precision floating point register to the given value. */
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void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
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int(reg_idx), (uint64_t)val);
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#if THE_ISA == ALPHA_ISA
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if (reg_idx != TheISA::ZeroReg)
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#endif
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floatRegFile[reg_idx].d = val;
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}
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/** Sets a double precision floating point register to the given value. */
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void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
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int(reg_idx), (uint64_t)val);
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#if THE_ISA == ALPHA_ISA
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if (reg_idx != TheISA::ZeroReg)
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#endif
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floatRegFile[reg_idx].d = val;
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}
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/** Sets a floating point register to the given integer value. */
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void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
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int(reg_idx), (uint64_t)val);
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floatRegFile[reg_idx].q = val;
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}
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void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
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int(reg_idx), (uint64_t)val);
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floatRegFile[reg_idx].q = val;
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}
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MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id)
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{
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return miscRegs[thread_id].readRegNoEffect(misc_reg);
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}
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MiscReg readMiscReg(int misc_reg, unsigned thread_id)
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{
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return miscRegs[thread_id].readReg(misc_reg, cpu->tcBase(thread_id));
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}
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void setMiscRegNoEffect(int misc_reg,
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const MiscReg &val, unsigned thread_id)
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{
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miscRegs[thread_id].setRegNoEffect(misc_reg, val);
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}
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void setMiscReg(int misc_reg, const MiscReg &val,
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unsigned thread_id)
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{
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miscRegs[thread_id].setReg(misc_reg, val,
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cpu->tcBase(thread_id));
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}
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public:
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/** (signed) integer register file. */
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IntReg *intRegFile;
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/** Floating point register file. */
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PhysFloatReg *floatRegFile;
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/** Miscellaneous register file. */
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MiscRegFile miscRegs[Impl::MaxThreads];
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#if FULL_SYSTEM
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private:
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int intrflag; // interrupt flag
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#endif
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private:
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/** CPU pointer. */
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O3CPU *cpu;
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public:
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/** Number of physical integer registers. */
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unsigned numPhysicalIntRegs;
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/** Number of physical floating point registers. */
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unsigned numPhysicalFloatRegs;
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};
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template <class Impl>
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PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
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unsigned _numPhysicalFloatRegs)
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: cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs),
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numPhysicalFloatRegs(_numPhysicalFloatRegs)
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{
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intRegFile = new IntReg[numPhysicalIntRegs];
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floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
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for (int i = 0; i < Impl::MaxThreads; ++i) {
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miscRegs[i].clear();
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}
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memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
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memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
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}
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#endif
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