.. |
probe
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sim: Automatically unregister probe listeners
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2014-09-09 04:36:43 -04:00 |
arguments.cc
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GetArgument: Rework getArgument so that X86_FS compiles again.
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2010-10-15 23:57:06 -07:00 |
arguments.hh
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arch: Resurrect the NOISA build target and rename it NULL
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2013-09-04 13:22:57 -04:00 |
async.cc
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base: Fix race in PollQueue and remove SIGALRM workaround
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2013-11-29 14:36:10 +01:00 |
async.hh
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base: Fix race in PollQueue and remove SIGALRM workaround
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2013-11-29 14:36:10 +01:00 |
BaseTLB.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
byteswap.hh
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gcc: Clean-up of non-C++0x compliant code, first steps
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2012-03-19 06:36:09 -04:00 |
clock_domain.cc
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energy: Small extentions and fixes for DVFS handler
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2014-06-16 14:59:44 +01:00 |
clock_domain.hh
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energy: Small extentions and fixes for DVFS handler
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2014-06-16 14:59:44 +01:00 |
ClockDomain.py
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power: Add basic DVFS support for gem5
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2014-06-30 13:56:06 -04:00 |
clocked_object.hh
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sim: More rigorous clocking comments
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2014-06-09 22:01:16 -05:00 |
ClockedObject.py
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sim: Add the notion of clock domains to all ClockedObjects
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2013-06-27 05:49:49 -04:00 |
core.cc
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
core.hh
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
debug.cc
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
debug.hh
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sim: Clarify the difference between tracing and debugging
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2013-11-01 11:56:13 -04:00 |
drain.cc
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sim: Move the draining interface into a separate base class
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2012-11-02 11:32:01 -05:00 |
drain.hh
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scons: Add warning for missing declarations
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2013-02-19 05:56:07 -05:00 |
dvfs_handler.cc
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energy: Small extentions and fixes for DVFS handler
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2014-06-16 14:59:44 +01:00 |
dvfs_handler.hh
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energy: Tighter checking of levels for DFS systems
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2014-08-12 19:00:44 +01:00 |
DVFSHandler.py
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power: Add basic DVFS support for gem5
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2014-06-30 13:56:06 -04:00 |
eventq.cc
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misc: Fix a bunch of minor issues identified by static analysis
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2014-09-27 09:08:29 -04:00 |
eventq.hh
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misc: Fix a bunch of minor issues identified by static analysis
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2014-09-27 09:08:29 -04:00 |
eventq_impl.hh
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
fault_fwd.hh
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cpu: Don't forward declare RefCountingPtr
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2014-08-13 06:57:26 -04:00 |
faults.cc
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arch: Use const StaticInstPtr references where possible
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2014-09-27 09:08:36 -04:00 |
faults.hh
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arch: Use const StaticInstPtr references where possible
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2014-09-27 09:08:36 -04:00 |
full_system.hh
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clang: Fix recently introduced clang compilation errors
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2012-03-19 06:35:04 -04:00 |
global_event.cc
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sim: Fix resource leak in BaseGlobalEvent
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2014-09-09 04:36:32 -04:00 |
global_event.hh
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sim: Fix resource leak in BaseGlobalEvent
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2014-09-09 04:36:32 -04:00 |
init.cc
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sim: Use correct unit for abort message
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2014-04-23 05:18:27 -04:00 |
init.hh
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scons: Add warning for missing declarations
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2013-02-19 05:56:07 -05:00 |
insttracer.hh
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cpu: Allow setWhen on trace objects
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2014-05-09 18:58:47 -04:00 |
InstTracer.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
main.cc
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libm5: Create a libm5 static library for embedding m5.
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2008-08-03 18:19:54 -07:00 |
microcode_rom.hh
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CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
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2008-10-12 15:59:21 -07:00 |
process.cc
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alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
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2014-09-20 17:18:35 -04:00 |
process.hh
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mem: adding architectural page table support for SE mode
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2014-08-28 10:11:44 -05:00 |
Process.py
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mem: adding architectural page table support for SE mode
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2014-08-28 10:11:44 -05:00 |
process_impl.hh
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MEM: Make port proxies use references rather than pointers
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2012-02-24 11:45:30 -05:00 |
pseudo_inst.cc
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sim: added option to serialize SimLoopExitEvent
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2013-10-31 13:41:13 -05:00 |
pseudo_inst.hh
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sim: Add a helper function to execute pseudo instructions
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2013-04-22 13:20:32 -04:00 |
root.cc
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
root.hh
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sim: Provide a framework for detecting out of data checkpoints and migrating them.
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2012-06-05 01:23:10 -04:00 |
Root.py
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
SConscript
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config: Add SubSystem container for simobjects
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2014-08-10 05:39:16 -04:00 |
serialize.cc
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base: Clean up redundant string functions and use C++11
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2014-09-20 17:17:49 -04:00 |
serialize.hh
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arm: use condition code registers for ARM ISA
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2014-04-29 16:05:02 -05:00 |
sim_events.cc
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
sim_events.hh
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
sim_exit.hh
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
sim_object.cc
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misc: Fix issues identified by static analysis
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2014-10-01 08:05:54 -04:00 |
sim_object.hh
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misc: Fix issues identified by static analysis
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2014-10-01 08:05:54 -04:00 |
simulate.cc
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sim: Add the ability to lock and migrate between event queues
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2014-04-03 11:22:49 +02:00 |
simulate.hh
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
stat_control.cc
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style: Fix line continuation, especially in debug messages
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2014-09-12 10:22:47 -04:00 |
stat_control.hh
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scons: Add warning for missing declarations
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2013-02-19 05:56:07 -05:00 |
stats.hh
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stats: make simTicks and simFreq accessible from stats.hh
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2010-04-18 13:23:25 -07:00 |
sub_system.cc
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config: Add SubSystem container for simobjects
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2014-08-10 05:39:16 -04:00 |
sub_system.hh
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config: Add SubSystem container for simobjects
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2014-08-10 05:39:16 -04:00 |
SubSystem.py
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config: Add SubSystem container for simobjects
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2014-08-10 05:39:16 -04:00 |
syscall_emul.cc
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arch: Cleanup unused ISA traits constants
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2014-09-03 07:42:21 -04:00 |
syscall_emul.hh
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arch: Cleanup unused ISA traits constants
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2014-09-03 07:42:21 -04:00 |
syscallreturn.hh
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syscall emulation: clean up & comment SyscallReturn
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2014-05-12 14:23:31 -07:00 |
system.cc
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misc: Restore ostream flags where needed
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2014-09-19 10:35:09 -04:00 |
system.hh
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sim: remove unused MemoryModeStrings array
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2014-07-18 22:05:51 -07:00 |
System.py
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sim: remove kernel mapping check for baremetal workloads
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2014-08-13 06:57:35 -04:00 |
ticked_object.cc
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sim: Fix checkpoint restore for Ticked
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2014-09-03 07:42:25 -04:00 |
ticked_object.hh
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cpu: `Minor' in-order CPU model
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2014-07-23 16:09:04 -05:00 |
TickedObject.py
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cpu: `Minor' in-order CPU model
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2014-07-23 16:09:04 -05:00 |
tlb.cc
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arch: Create a method to finalize physical addresses
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2013-06-03 13:55:41 +02:00 |
tlb.hh
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arch: Pass faults by const reference where possible
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2014-09-19 10:35:18 -04:00 |
voltage_domain.cc
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energy: Small extentions and fixes for DVFS handler
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2014-06-16 14:59:44 +01:00 |
voltage_domain.hh
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energy: Tighter checking of levels for DFS systems
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2014-08-12 19:00:44 +01:00 |
VoltageDomain.py
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power: Add basic DVFS support for gem5
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2014-06-30 13:56:06 -04:00 |
vptr.hh
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MEM: Make port proxies use references rather than pointers
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2012-02-24 11:45:30 -05:00 |