.. |
cache
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cache: Allow main memory to be at disjoint address ranges.
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2012-03-09 09:59:25 -05:00 |
config
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Fixes to get prefetching working again.
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2009-02-16 08:56:40 -08:00 |
protocol
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build scripts: Made minor modifications to reduce build overhead time.
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2012-03-06 19:07:41 -08:00 |
ruby
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Ruby: Rename RubyPort::sendTiming to avoid overriding base class
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2012-03-02 09:16:50 -05:00 |
slicc
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Ruby: Add infrastructure for recording cache contents
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2012-01-11 13:29:15 -06:00 |
bridge.cc
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MEM: Move port creation to the memory object(s) construction
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2012-02-24 11:43:53 -05:00 |
bridge.hh
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MEM: Move port creation to the memory object(s) construction
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2012-02-24 11:43:53 -05:00 |
Bridge.py
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MEM: Introduce the master/slave port roles in the Python classes
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2012-02-13 06:43:09 -05:00 |
bus.cc
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MEM: Move port creation to the memory object(s) construction
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2012-02-24 11:43:53 -05:00 |
bus.hh
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MEM: Move port creation to the memory object(s) construction
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2012-02-24 11:43:53 -05:00 |
Bus.py
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MEM: Introduce the master/slave port roles in the Python classes
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2012-02-13 06:43:09 -05:00 |
dram.cc
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Replace curTick global variable with accessor functions.
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2011-01-07 21:50:29 -08:00 |
dram.hh
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stats: Fix all stats usages to deal with template fixes
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2009-03-05 19:09:53 -08:00 |
fs_translating_port_proxy.cc
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MEM: Make all the port proxy members const
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2012-02-29 04:47:51 -05:00 |
fs_translating_port_proxy.hh
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MEM: Make all the port proxy members const
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2012-02-29 04:47:51 -05:00 |
mem_object.cc
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MEM: Remove Port removeConn and MemObject deletePortRefs
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2012-01-17 12:55:09 -06:00 |
mem_object.hh
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MEM: Remove Port removeConn and MemObject deletePortRefs
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2012-01-17 12:55:09 -06:00 |
MemObject.py
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
mport.cc
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MEM: Prepare mport for master/slave split
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2012-02-24 11:50:15 -05:00 |
mport.hh
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MEM: Prepare mport for master/slave split
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2012-02-24 11:50:15 -05:00 |
packet.cc
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MemCmd: Add a command for invalidation requests to LSQ
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2012-01-23 11:07:11 -06:00 |
packet.hh
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clang: Enable compiling gem5 using clang 2.9 and 3.0
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2012-01-31 12:05:52 -05:00 |
packet_access.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
page_table.cc
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Another merge with the main repository.
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2012-01-07 02:16:37 -08:00 |
page_table.hh
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SE/FS: Get rid of includes of config/full_system.hh.
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2011-11-18 02:20:22 -08:00 |
physical.cc
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MEM: Move port creation to the memory object(s) construction
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2012-02-24 11:43:53 -05:00 |
physical.hh
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Mem: Add simple bandwidth stats to PhysicalMemory
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2012-01-25 17:18:25 +00:00 |
PhysicalMemory.py
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MEM: Introduce the master/slave port roles in the Python classes
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2012-02-13 06:43:09 -05:00 |
port.cc
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MEM: Move all read/write blob functions from Port to PortProxy
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2012-02-24 11:46:39 -05:00 |
port.hh
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MEM: Move all read/write blob functions from Port to PortProxy
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2012-02-24 11:46:39 -05:00 |
port_proxy.cc
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MEM: Make all the port proxy members const
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2012-02-29 04:47:51 -05:00 |
port_proxy.hh
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MEM: Make all the port proxy members const
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2012-02-29 04:47:51 -05:00 |
request.hh
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mem: fix cache stats to use request ids correctly
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2012-02-12 16:07:39 -06:00 |
SConscript
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MEM: Move all read/write blob functions from Port to PortProxy
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2012-02-24 11:46:39 -05:00 |
se_translating_port_proxy.cc
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MEM: Make all the port proxy members const
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2012-02-29 04:47:51 -05:00 |
se_translating_port_proxy.hh
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MEM: Make all the port proxy members const
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2012-02-29 04:47:51 -05:00 |
tport.cc
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MEM: Simplify cache ports preparing for master/slave split
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2012-02-24 11:52:49 -05:00 |
tport.hh
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MEM: Simplify cache ports preparing for master/slave split
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2012-02-24 11:52:49 -05:00 |