gem5/src/mem/cache
Andreas Hansson de34e49d15 MEM: Simplify ports by removing EventManager
This patch removes the inheritance of EventManager from the ports and
moves all responsibility for event queues to the owner. Eventually the
event manager should be the interface block, which could either be the
structural owner or a subblock like a LSQ in the O3 CPU for example.
2012-01-17 12:55:09 -06:00
..
prefetch Fix build for gcc-4.2 opt/fast 2011-09-01 15:25:54 -07:00
tags GCC: Get everything working with gcc 4.6.1. 2011-10-31 01:09:44 -07:00
base.cc MEM: Simplify ports by removing EventManager 2012-01-17 12:55:09 -06:00
base.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
BaseCache.py Mem: Fix issue with dirty block being lost when entire block transferred to non-cache. 2011-03-17 19:20:19 -05:00
blk.cc Fix #include lines for renamed cache files. 2008-02-10 14:45:25 -08:00
blk.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
builder.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
cache.cc remove the totally obsolete split cache 2008-10-23 16:11:28 -04:00
cache.hh MEM: Differentiate functional cache accesses from CPU and memory 2012-01-17 12:55:07 -06:00
cache_impl.hh MEM: Simplify ports by removing EventManager 2012-01-17 12:55:09 -06:00
mshr.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
mshr.hh Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
mshr_queue.cc cache: coherence protocol enhancements & bug fixes 2010-09-09 14:40:18 -04:00
mshr_queue.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
SConscript scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00