13ef7a5647
This patch changes the functionalAccess member function in the cache model such that it is aware of what port the access came from, i.e. if it came from the CPU side or from the memory side. By adding this information, it is possible to respect the 'forwardSnoops' flag for snooping requests coming from the memory side and not forward them. This fixes an outstanding issue with the IO bus getting accesses that have no valid destination port and also cleans up future changes to the bus model.
340 lines
11 KiB
C++
340 lines
11 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Dave Greene
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* Steve Reinhardt
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* Ron Dreslinski
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*/
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/**
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* @file
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* Describes a cache based on template policies.
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*/
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#ifndef __CACHE_HH__
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#define __CACHE_HH__
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#include "base/misc.hh" // fatal, panic, and warn
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#include "mem/cache/base.hh"
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#include "mem/cache/blk.hh"
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#include "mem/cache/mshr.hh"
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#include "sim/eventq.hh"
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//Forward decleration
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class BasePrefetcher;
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/**
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* A template-policy based cache. The behavior of the cache can be altered by
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* supplying different template policies. TagStore handles all tag and data
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* storage @sa TagStore.
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*/
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template <class TagStore>
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class Cache : public BaseCache
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{
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public:
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/** Define the type of cache block to use. */
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typedef typename TagStore::BlkType BlkType;
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/** A typedef for a list of BlkType pointers. */
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typedef typename TagStore::BlkList BlkList;
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protected:
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class CpuSidePort : public CachePort
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{
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public:
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CpuSidePort(const std::string &_name,
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Cache<TagStore> *_cache,
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const std::string &_label);
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// BaseCache::CachePort just has a BaseCache *; this function
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// lets us get back the type info we lost when we stored the
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// cache pointer there.
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Cache<TagStore> *myCache() {
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return static_cast<Cache<TagStore> *>(cache);
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}
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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bool &snoop);
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virtual bool recvTiming(PacketPtr pkt);
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virtual Tick recvAtomic(PacketPtr pkt);
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virtual void recvFunctional(PacketPtr pkt);
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};
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class MemSidePort : public CachePort
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{
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public:
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MemSidePort(const std::string &_name,
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Cache<TagStore> *_cache,
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const std::string &_label);
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// BaseCache::CachePort just has a BaseCache *; this function
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// lets us get back the type info we lost when we stored the
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// cache pointer there.
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Cache<TagStore> *myCache() {
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return static_cast<Cache<TagStore> *>(cache);
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}
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void sendPacket();
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void processSendEvent();
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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bool &snoop);
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virtual bool recvTiming(PacketPtr pkt);
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virtual void recvRetry();
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virtual Tick recvAtomic(PacketPtr pkt);
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virtual void recvFunctional(PacketPtr pkt);
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typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
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SendEvent;
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};
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/** Tag and data Storage */
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TagStore *tags;
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/** Prefetcher */
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BasePrefetcher *prefetcher;
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/** Temporary cache block for occasional transitory use */
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BlkType *tempBlock;
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/**
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* This cache should allocate a block on a line-sized write miss.
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*/
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const bool doFastWrites;
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/**
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* Notify the prefetcher on every access, not just misses.
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*/
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const bool prefetchOnAccess;
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/**
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* Does all the processing necessary to perform the provided request.
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* @param pkt The memory request to perform.
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* @param lat The latency of the access.
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* @param writebacks List for any writebacks that need to be performed.
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* @param update True if the replacement data should be updated.
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* @return Boolean indicating whether the request was satisfied.
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*/
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bool access(PacketPtr pkt, BlkType *&blk,
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int &lat, PacketList &writebacks);
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/**
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*Handle doing the Compare and Swap function for SPARC.
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*/
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void cmpAndSwap(BlkType *blk, PacketPtr pkt);
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/**
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* Find a block frame for new block at address addr, assuming that
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* the block is not currently in the cache. Append writebacks if
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* any to provided packet list. Return free block frame. May
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* return NULL if there are no replaceable blocks at the moment.
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*/
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BlkType *allocateBlock(Addr addr, PacketList &writebacks);
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/**
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* Populates a cache block and handles all outstanding requests for the
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* satisfied fill request. This version takes two memory requests. One
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* contains the fill data, the other is an optional target to satisfy.
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* @param pkt The memory request with the fill data.
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* @param blk The cache block if it already exists.
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* @param writebacks List for any writebacks that need to be performed.
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* @return Pointer to the new cache block.
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*/
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BlkType *handleFill(PacketPtr pkt, BlkType *blk,
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PacketList &writebacks);
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void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
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bool deferred_response = false,
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bool pending_downgrade = false);
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bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
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void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
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bool already_copied, bool pending_inval);
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/**
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* Sets the blk to the new state.
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* @param blk The cache block being snooped.
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* @param new_state The new coherence state for the block.
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*/
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void handleSnoop(PacketPtr ptk, BlkType *blk,
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bool is_timing, bool is_deferred, bool pending_inval);
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/**
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* Create a writeback request for the given block.
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* @param blk The block to writeback.
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* @return The writeback request for the block.
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*/
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PacketPtr writebackBlk(BlkType *blk);
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public:
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/** Instantiates a basic cache object. */
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Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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virtual void deletePortRefs(Port *p);
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void regStats();
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/**
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* Performs the access specified by the request.
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* @param pkt The request to perform.
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* @return The result of the access.
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*/
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bool timingAccess(PacketPtr pkt);
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/**
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* Performs the access specified by the request.
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* @param pkt The request to perform.
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* @return The result of the access.
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*/
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Tick atomicAccess(PacketPtr pkt);
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/**
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* Performs the access specified by the request.
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* @param pkt The request to perform.
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* @param fromCpuSide from the CPU side port or the memory side port
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*/
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void functionalAccess(PacketPtr pkt, bool fromCpuSide);
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/**
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* Handles a response (cache line fill/write ack) from the bus.
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* @param pkt The request being responded to.
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*/
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void handleResponse(PacketPtr pkt);
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/**
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* Snoops bus transactions to maintain coherence.
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* @param pkt The current bus transaction.
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*/
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void snoopTiming(PacketPtr pkt);
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/**
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* Snoop for the provided request in the cache and return the estimated
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* time of completion.
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* @param pkt The memory request to snoop
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* @return The estimated completion time.
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*/
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Tick snoopAtomic(PacketPtr pkt);
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/**
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* Squash all requests associated with specified thread.
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* intended for use by I-cache.
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* @param threadNum The thread to squash.
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*/
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void squash(int threadNum);
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/**
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* Generate an appropriate downstream bus request packet for the
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* given parameters.
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* @param cpu_pkt The upstream request that needs to be satisfied.
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* @param blk The block currently in the cache corresponding to
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* cpu_pkt (NULL if none).
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* @param needsExclusive Indicates that an exclusive copy is required
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* even if the request in cpu_pkt doesn't indicate that.
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* @return A new Packet containing the request, or NULL if the
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* current request in cpu_pkt should just be forwarded on.
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*/
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PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
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bool needsExclusive);
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/**
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* Return the next MSHR to service, either a pending miss from the
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* mshrQueue, a buffered write from the write buffer, or something
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* from the prefetcher. This function is responsible for
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* prioritizing among those sources on the fly.
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*/
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MSHR *getNextMSHR();
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/**
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* Selects an outstanding request to service. Called when the
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* cache gets granted the downstream bus in timing mode.
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* @return The request to service, NULL if none found.
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*/
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PacketPtr getTimingPacket();
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/**
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* Marks a request as in service (sent on the bus). This can have side
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* effect since storage for no response commands is deallocated once they
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* are successfully sent.
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* @param pkt The request that was sent on the bus.
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*/
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void markInService(MSHR *mshr, PacketPtr pkt = 0);
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/**
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* Perform the given writeback request.
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* @param pkt The writeback request.
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*/
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void doWriteback(PacketPtr pkt);
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/**
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* Return whether there are any outstanding misses.
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*/
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bool outstandingMisses() const
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{
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return mshrQueue.allocated != 0;
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}
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CacheBlk *findBlock(Addr addr) {
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return tags->findBlock(addr);
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}
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bool inCache(Addr addr) {
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return (tags->findBlock(addr) != 0);
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}
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bool inMissQueue(Addr addr) {
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return (mshrQueue.findMatch(addr) != 0);
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}
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/**
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* Find next request ready time from among possible sources.
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*/
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Tick nextMSHRReadyTime();
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};
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#endif // __CACHE_HH__
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