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gem5/src/cpu
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Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E) dbeabedaf0 branch predictor: move out of o3 and inorder cpus 
This patch moves the branch predictor files in the o3 and inorder directories
to src/cpu/pred. This allows sharing the branch predictor across different
cpu models.

This patch was originally posted by Timothy Jones in July 2010
but never made it to the repository.

--HG--
rename : src/cpu/o3/bpred_unit.cc => src/cpu/pred/bpred_unit.cc
rename : src/cpu/o3/bpred_unit.hh => src/cpu/pred/bpred_unit.hh
rename : src/cpu/o3/bpred_unit_impl.hh => src/cpu/pred/bpred_unit_impl.hh
rename : src/cpu/o3/sat_counter.hh => src/cpu/pred/sat_counter.hh
2013-01-24 12:28:51 -06:00
..
checker cpu: Implement a flat register interface in thread contexts 2013-01-07 13:05:44 -05:00
inorder branch predictor: move out of o3 and inorder cpus 2013-01-24 12:28:51 -06:00
nocpu SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
o3 branch predictor: move out of o3 and inorder cpus 2013-01-24 12:28:51 -06:00
ozone cpu: Rename defer_registration->switched_out 2013-01-07 13:05:45 -05:00
pred branch predictor: move out of o3 and inorder cpus 2013-01-24 12:28:51 -06:00
simple base simple cpu: removes commented out code about cache ops 2013-01-12 22:11:16 -06:00
testers ruby: remove calls to g_system_ptr->getTime() 2013-01-17 13:10:12 -06:00
trace includes: sort all includes 2011-04-15 10:44:06 -07:00
activity.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
activity.hh Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
base.cc cpu: Unify the serialization code for all of the CPU models 2013-01-07 13:05:52 -05:00
base.hh cpu: Unify the serialization code for all of the CPU models 2013-01-07 13:05:52 -05:00
base_dyn_inst.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
base_dyn_inst_impl.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
BaseCPU.py branch predictor: move out of o3 and inorder cpus 2013-01-24 12:28:51 -06:00
CheckerCPU.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
decode_cache.hh ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
dummy_checker.cc arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
dummy_checker.hh cpu: Add header files for checker CPUs 2012-11-02 11:32:01 -05:00
DummyChecker.py cpu: Add header files for checker CPUs 2012-11-02 11:32:01 -05:00
exec_context.hh SE/FS: Expose the same methods on the CPUs in SE and FS modes. 2011-11-01 04:01:13 -07:00
exetrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
exetrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
ExeTracer.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
FuncUnit.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
inst_seq.hh build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
inteltrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
inteltrace.hh sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
IntelTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
intr_control.cc SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 2011-11-18 01:33:28 -08:00
intr_control.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
IntrControl.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
legiontrace.cc Decoder: Remove the thread context get/set from the decoder. 2013-01-04 19:00:45 -06:00
legiontrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
LegionTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
nativetrace.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
nativetrace.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
NativeTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
op_class.hh CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
pc_event.cc ARM: dump stats and process info on context switches 2012-11-02 11:32:01 -05:00
pc_event.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
profile.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
profile.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
quiesce_event.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
quiesce_event.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
SConscript cpu: Add header files for checker CPUs 2012-11-02 11:32:01 -05:00
simple_thread.cc x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch 2013-01-22 00:10:10 -06:00
simple_thread.hh x86: Changes to decoder, corrects 9376 2013-01-12 22:09:48 -06:00
smt.hh includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
static_inst.cc Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
static_inst.hh sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
static_inst_fwd.hh StaticInst: Merge StaticInst and StaticInstBase. 2011-09-09 02:40:11 -07:00
thread_context.cc cpu: Fix broken thread context handover 2013-01-07 13:05:46 -05:00
thread_context.hh cpu: Fix broken thread context handover 2013-01-07 13:05:46 -05:00
thread_state.cc cpu: added assertions to ensure the correct proxies are used 2012-07-10 22:51:53 -07:00
thread_state.hh cpu: added assertions to ensure the correct proxies are used 2012-07-10 22:51:53 -07:00
timebuf.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
translation.hh ARM: Squash outstanding walks when instructions are squashed. 2012-09-25 11:49:40 -05:00