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gem5/src/sim
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Andrew Bardsley d8502ee46d config: Add a --without-python option to build process 
Add the ability to build libgem5 without embedded Python or the
ability to configure with Python.

This is a prelude to a patch to allow config.ini files to be loaded
into libgem5 using only C++ which would make embedding gem5 within
other simulation systems easier.

This adds a few registration interfaces to things which cross
between Python and C++.  Namely: stats dumping and SimObject resolving
2014-10-16 05:49:32 -04:00
..
probe sim: Automatically unregister probe listeners 2014-09-09 04:36:43 -04:00
arguments.cc GetArgument: Rework getArgument so that X86_FS compiles again. 2010-10-15 23:57:06 -07:00
arguments.hh arch: Resurrect the NOISA build target and rename it NULL 2013-09-04 13:22:57 -04:00
async.cc base: Fix race in PollQueue and remove SIGALRM workaround 2013-11-29 14:36:10 +01:00
async.hh base: Fix race in PollQueue and remove SIGALRM workaround 2013-11-29 14:36:10 +01:00
BaseTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
byteswap.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
clock_domain.cc energy: Small extentions and fixes for DVFS handler 2014-06-16 14:59:44 +01:00
clock_domain.hh energy: Small extentions and fixes for DVFS handler 2014-06-16 14:59:44 +01:00
ClockDomain.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
clocked_object.hh sim: More rigorous clocking comments 2014-06-09 22:01:16 -05:00
ClockedObject.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
core.cc sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
core.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
debug.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
debug.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
drain.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
drain.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
dvfs_handler.cc energy: Small extentions and fixes for DVFS handler 2014-06-16 14:59:44 +01:00
dvfs_handler.hh energy: Tighter checking of levels for DFS systems 2014-08-12 19:00:44 +01:00
DVFSHandler.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
eventq.cc misc: Fix a bunch of minor issues identified by static analysis 2014-09-27 09:08:29 -04:00
eventq.hh misc: Fix a bunch of minor issues identified by static analysis 2014-09-27 09:08:29 -04:00
eventq_impl.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
fault_fwd.hh cpu: Don't forward declare RefCountingPtr 2014-08-13 06:57:26 -04:00
faults.cc arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
faults.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
full_system.hh clang: Fix recently introduced clang compilation errors 2012-03-19 06:35:04 -04:00
global_event.cc sim: Fix resource leak in BaseGlobalEvent 2014-09-09 04:36:32 -04:00
global_event.hh sim: Fix resource leak in BaseGlobalEvent 2014-09-09 04:36:32 -04:00
init.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
init.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
init_signals.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
init_signals.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
insttracer.hh cpu: Allow setWhen on trace objects 2014-05-09 18:58:47 -04:00
InstTracer.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
main.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
process.cc alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate 2014-09-20 17:18:35 -04:00
process.hh mem: adding architectural page table support for SE mode 2014-08-28 10:11:44 -05:00
Process.py mem: adding architectural page table support for SE mode 2014-08-28 10:11:44 -05:00
process_impl.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
pseudo_inst.cc sim: added option to serialize SimLoopExitEvent 2013-10-31 13:41:13 -05:00
pseudo_inst.hh sim: Add a helper function to execute pseudo instructions 2013-04-22 13:20:32 -04:00
py_interact.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
py_interact.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
root.cc sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
root.hh sim: Provide a framework for detecting out of data checkpoints and migrating them. 2012-06-05 01:23:10 -04:00
Root.py sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
SConscript config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
serialize.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
serialize.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
sim_events.cc sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
sim_events.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
sim_exit.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
sim_object.cc misc: Fix issues identified by static analysis 2014-10-01 08:05:54 -04:00
sim_object.hh misc: Fix issues identified by static analysis 2014-10-01 08:05:54 -04:00
simulate.cc sim: Add the ability to lock and migrate between event queues 2014-04-03 11:22:49 +02:00
simulate.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
stat_control.cc style: Fix line continuation, especially in debug messages 2014-09-12 10:22:47 -04:00
stat_control.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
stat_register.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
stat_register.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
stats.hh stats: make simTicks and simFreq accessible from stats.hh 2010-04-18 13:23:25 -07:00
sub_system.cc config: Add SubSystem container for simobjects 2014-08-10 05:39:16 -04:00
sub_system.hh config: Add SubSystem container for simobjects 2014-08-10 05:39:16 -04:00
SubSystem.py config: Add SubSystem container for simobjects 2014-08-10 05:39:16 -04:00
syscall_emul.cc arch: Cleanup unused ISA traits constants 2014-09-03 07:42:21 -04:00
syscall_emul.hh arch: Cleanup unused ISA traits constants 2014-09-03 07:42:21 -04:00
syscallreturn.hh syscall emulation: clean up & comment SyscallReturn 2014-05-12 14:23:31 -07:00
system.cc misc: Restore ostream flags where needed 2014-09-19 10:35:09 -04:00
system.hh sim: remove unused MemoryModeStrings array 2014-07-18 22:05:51 -07:00
System.py sim: remove kernel mapping check for baremetal workloads 2014-08-13 06:57:35 -04:00
ticked_object.cc sim: Fix checkpoint restore for Ticked 2014-09-03 07:42:25 -04:00
ticked_object.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
TickedObject.py cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
tlb.cc arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
tlb.hh arch: Pass faults by const reference where possible 2014-09-19 10:35:18 -04:00
voltage_domain.cc energy: Small extentions and fixes for DVFS handler 2014-06-16 14:59:44 +01:00
voltage_domain.hh energy: Tighter checking of levels for DFS systems 2014-08-12 19:00:44 +01:00
VoltageDomain.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
vptr.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00