..
checker
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
inorder
cpu: Move the branch predictor out of the BaseCPU
2013-09-04 13:22:56 -04:00
kvm
kvm: Correctly handle the return value from handleIpr(Read|Write)
2013-09-19 17:55:04 +02:00
nocpu
SCons: Support building without an ISA
2010-11-19 18:00:39 -06:00
o3
cpu: Dynamically instantiate O3 CPU LSQUnits
2013-09-11 15:34:50 -05:00
ozone
cpu: Accurately count idle cycles for simple cpu
2013-08-19 03:52:35 -04:00
pred
cpu: remove local/globalHistoryBits params from branch pred
2013-05-14 18:39:47 -04:00
simple
cpu: Fix timing CPU isDrained comment formatting
2013-08-20 11:21:27 -04:00
testers
cpu: Fix TrafficGen trace playback
2013-08-19 03:52:32 -04:00
activity.cc
Fix: Address a few benign memory leaks
2012-07-09 12:35:30 -04:00
activity.hh
Fix: Address a few benign memory leaks
2012-07-09 12:35:30 -04:00
base.cc
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
base.hh
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
base_dyn_inst.hh
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
base_dyn_inst_impl.hh
O3: Clean up the O3 structures and try to pack them a bit better.
2012-06-05 01:23:09 -04:00
BaseCPU.py
cpu: Move the branch predictor out of the BaseCPU
2013-09-04 13:22:56 -04:00
CheckerCPU.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
cpuevent.cc
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
2006-06-06 17:32:21 -04:00
cpuevent.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
decode_cache.hh
ISA,CPU: Generalize and split out the components of the decode cache.
2012-05-26 13:45:12 -07:00
dummy_checker.cc
sim: Add the notion of clock domains to all ClockedObjects
2013-06-27 05:49:49 -04:00
dummy_checker.hh
cpu: Add header files for checker CPUs
2012-11-02 11:32:01 -05:00
DummyChecker.py
cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
2013-02-15 17:40:08 -05:00
exec_context.hh
SE/FS: Expose the same methods on the CPUs in SE and FS modes.
2011-11-01 04:01:13 -07:00
exetrace.cc
debug : Fixes the issue wherein Debug symbols were not getting dumped into trace files for SE mode
2013-07-15 11:08:34 -04:00
exetrace.hh
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
ExeTracer.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
func_unit.cc
params: Deprecate old-style constructors; update most SimObject constructors.
2007-08-30 15:16:59 -04:00
func_unit.hh
Param: Transition to Cycles for relevant parameters
2012-09-07 12:34:38 -04:00
FuncUnit.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
inst_seq.hh
build: fix compile problems pointed out by gcc 4.4
2009-11-04 16:57:01 -08:00
inteltrace.cc
gcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 06:36:09 -04:00
inteltrace.hh
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
IntelTrace.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
intr_control.cc
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
2011-11-18 01:33:28 -08:00
intr_control.hh
arch: Header clean up for NOISA resurrection
2013-09-04 13:22:55 -04:00
intr_control_noisa.cc
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
IntrControl.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
legiontrace.cc
Decoder: Remove the thread context get/set from the decoder.
2013-01-04 19:00:45 -06:00
legiontrace.hh
scons: Add warning for missing declarations
2013-02-19 05:56:07 -05:00
LegionTrace.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
m5legion_interface.h
add fsr to the list of registers we are interested in
2007-01-30 18:27:04 -05:00
nativetrace.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
nativetrace.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
NativeTrace.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
op_class.hh
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
2010-11-15 14:04:04 -06:00
pc_event.cc
arm: Enable support for triggering a sim panic on kernel panics
2013-04-22 13:20:31 -04:00
pc_event.hh
arm: Enable support for triggering a sim panic on kernel panics
2013-04-22 13:20:31 -04:00
profile.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
profile.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
quiesce_event.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
quiesce_event.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
SConscript
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
simple_thread.cc
x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch
2013-01-22 00:10:10 -06:00
simple_thread.hh
x86: Changes to decoder, corrects 9376
2013-01-12 22:09:48 -06:00
smt.hh
includes: fix up code after sorting
2011-04-15 10:44:14 -07:00
static_inst.cc
Decode: Pull instruction decoding out of the StaticInst class into its own.
2011-09-09 02:30:01 -07:00
static_inst.hh
arch: Header clean up for NOISA resurrection
2013-09-04 13:22:55 -04:00
static_inst_fwd.hh
StaticInst: Merge StaticInst and StaticInstBase.
2011-09-09 02:40:11 -07:00
thread_context.cc
cpu: Fix broken thread context handover
2013-01-07 13:05:46 -05:00
thread_context.hh
cpu: Fix broken thread context handover
2013-01-07 13:05:46 -05:00
thread_state.cc
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
thread_state.hh
cpu: added assertions to ensure the correct proxies are used
2012-07-10 22:51:53 -07:00
timebuf.hh
Move sched_list.hh and timebuf.hh from src/base to src/cpu.
2011-01-03 14:35:47 -08:00
translation.hh
ARM: Squash outstanding walks when instructions are squashed.
2012-09-25 11:49:40 -05:00