.. |
base_dyn_inst.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
bpred_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
bpred_unit.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
bpred_unit_impl.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
checker_builder.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
comm.hh
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O3: When squashing, restore the macroop that should be used for fetching.
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2011-08-14 17:41:34 -07:00 |
commit.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
commit.hh
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includes: fix up code after sorting
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2011-04-15 10:44:14 -07:00 |
commit_impl.hh
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Fix bugs due to interaction between SEV instructions and O3 pipeline
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2011-08-19 15:08:07 -05:00 |
cpu.cc
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O3: Get rid of the unused addToRemoveList function.
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2011-08-07 15:41:10 -07:00 |
cpu.hh
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Fix bugs due to interaction between SEV instructions and O3 pipeline
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2011-08-19 15:08:07 -05:00 |
cpu_builder.cc
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o3-smt: enforce numThreads parameter for SMT SE mode
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2009-07-25 00:50:27 -04:00 |
cpu_policy.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
decode.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
decode.hh
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Move sched_list.hh and timebuf.hh from src/base to src/cpu.
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2011-01-03 14:35:47 -08:00 |
decode_impl.hh
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O3: When squashing, restore the macroop that should be used for fetching.
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2011-08-14 17:41:34 -07:00 |
dep_graph.hh
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
dyn_inst.cc
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O3: Generaize the O3 IMPL class so it isn't split out by ISA.
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2008-10-09 00:10:02 -07:00 |
dyn_inst.hh
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O3: Add a pointer to the macroop for a microop in the dyninst.
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2011-08-14 04:08:14 -07:00 |
dyn_inst_impl.hh
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O3: Add a pointer to the macroop for a microop in the dyninst.
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2011-08-14 04:08:14 -07:00 |
fetch.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
fetch.hh
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O3: When squashing, restore the macroop that should be used for fetching.
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2011-08-14 17:41:34 -07:00 |
fetch_impl.hh
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O3: When squashing, restore the macroop that should be used for fetching.
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2011-08-14 17:41:34 -07:00 |
free_list.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
free_list.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
fu_pool.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
fu_pool.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
FuncUnitConfig.py
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
FUPool.py
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
iew.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
iew.hh
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O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.
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2011-05-23 10:40:19 -05:00 |
iew_impl.hh
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O3: Squash the violator and younger instructions instead not all insts.
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2011-08-19 15:08:05 -05:00 |
impl.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
inst_queue.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
inst_queue.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
inst_queue_impl.hh
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O3: Let squashed and deferred instructions issue.
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2011-08-07 15:41:07 -07:00 |
isa_specific.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
lsq.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
lsq.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
lsq_impl.hh
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o3: missing newlines on some dprintfs
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2011-06-10 22:15:32 -04:00 |
lsq_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
lsq_unit.hh
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O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.
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2011-08-16 02:46:57 -07:00 |
lsq_unit_impl.hh
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O3: Implement memory mapped IPRs for O3.
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2011-07-31 19:21:17 -07:00 |
mem_dep_unit.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
mem_dep_unit.hh
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LSQ: Add some better dprintfs for storeset predictor.
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2011-08-19 15:08:05 -05:00 |
mem_dep_unit_impl.hh
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LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
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2011-08-19 15:08:07 -05:00 |
O3Checker.py
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python: Move more code into m5.util allow SCons to use that code.
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2009-09-22 15:24:16 -07:00 |
O3CPU.py
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LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
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2011-08-19 15:08:07 -05:00 |
regfile.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
rename.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
rename.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
rename_impl.hh
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O3: Create a pipeline activity viewer for the O3 CPU model.
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2011-07-15 11:53:35 -05:00 |
rename_map.cc
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o3: missing newlines on some dprintfs
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2011-06-10 22:15:32 -04:00 |
rename_map.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
rob.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
rob.hh
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includes: fix up code after sorting
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2011-04-15 10:44:14 -07:00 |
rob_impl.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
sat_counter.cc
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
sat_counter.hh
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types: Move stuff for global types into src/base/types.hh
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2009-05-17 14:34:50 -07:00 |
SConscript
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scons: rename TraceFlags to DebugFlags
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2011-06-02 17:36:21 -07:00 |
SConsopts
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cpu_models: get rid of cpu_models.py and move the stuff into SCons
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2010-02-26 18:14:48 -08:00 |
scoreboard.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
scoreboard.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
store_set.cc
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LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
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2011-08-19 15:08:07 -05:00 |
store_set.hh
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LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
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2011-08-19 15:08:07 -05:00 |
thread_context.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
thread_context.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
thread_context_impl.hh
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Fix bugs due to interaction between SEV instructions and O3 pipeline
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2011-08-19 15:08:07 -05:00 |
thread_state.hh
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Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
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2009-07-08 23:02:22 -07:00 |