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Kevin Lim c23b23f4e7 Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU. 
base/traceflags.py:
build/SConstruct:
cpu/SConscript:
cpu/cpu_models.py:
    Add in Checker.
cpu/base.cc:
    Add in checker support.  Also XC status starts off as suspended.
cpu/base.hh:
    Add in checker.

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extra : convert_revision : 091b5cc83e837858adb681ef0137a0beb30bd1b2
2006-05-16 13:59:29 -04:00
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checker Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU. 2006-05-16 13:59:29 -04:00
memtest Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
o3 Small fixes to O3 model. 2006-05-11 15:39:02 -04:00
ozone Fixes for ozone CPU to successfully boot and run linux. 2006-05-11 19:18:36 -04:00
simple Fixes for the sampler. 2006-05-03 15:54:36 -04:00
trace Made Addr a global type 2006-02-21 03:38:21 -05:00
base.cc Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU. 2006-05-16 13:59:29 -04:00
base.hh Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU. 2006-05-16 13:59:29 -04:00
base_dyn_inst.cc Separate out result being ready and the instruction being complete. 2006-05-11 14:12:34 -04:00
base_dyn_inst.hh Fixes for ozone CPU to successfully boot and run linux. 2006-05-11 19:18:36 -04:00
cpu_exec_context.cc Sampling fixes related to the quiesce event. 2006-05-16 13:51:18 -04:00
cpu_exec_context.hh Sampling fixes related to the quiesce event. 2006-05-16 13:51:18 -04:00
cpu_models.py Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU. 2006-05-16 13:59:29 -04:00
exec_context.hh Sampling fixes related to the quiesce event. 2006-05-16 13:51:18 -04:00
exetrace.cc Allow the switching on and off of PC symbols for tracing. 2006-04-24 16:56:24 -04:00
exetrace.hh Allow the switching on and off of PC symbols for tracing. 2006-04-24 16:56:24 -04:00
inst_seq.hh Include option for disabling PC symbols. 2006-04-24 17:11:31 -04:00
intr_control.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
intr_control.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
pc_event.cc Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
pc_event.hh Made Addr a global type 2006-02-21 03:38:21 -05:00
profile.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
profile.hh Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
quiesce_event.cc Move quiesce event to its own class. 2006-04-22 18:11:54 -04:00
quiesce_event.hh Move quiesce event to its own class. 2006-04-22 18:11:54 -04:00
SConscript Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU. 2006-05-16 13:59:29 -04:00
smt.hh Many files: 2005-06-05 05:16:00 -04:00
static_inst.cc Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. 2006-02-19 02:34:37 -05:00
static_inst.hh Add some flags for the upcoming checker. 2006-05-16 13:48:05 -04:00
thread_state.hh Updates for O3 model. 2006-04-22 18:26:48 -04:00