gem5/src/sim
2010-11-08 13:58:25 -06:00
..
arguments.cc GetArgument: Rework getArgument so that X86_FS compiles again. 2010-10-15 23:57:06 -07:00
arguments.hh GetArgument: Rework getArgument so that X86_FS compiles again. 2010-10-15 23:57:06 -07:00
async.cc Factor code out of main.cc and main.i into a bunch of files 2007-03-02 22:24:00 -08:00
async.hh style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
BaseTLB.py TLB: Make all tlbs derive from a common base class in both python and C++. 2008-10-10 23:47:42 -07:00
byteswap.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
core.cc tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
core.hh tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
debug.cc debug: Move debug_break into src/base 2009-02-23 11:48:40 -08:00
debug.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
eventq.cc flags: add comment to avoid future deletions since code appears redundant. 2010-06-09 10:47:37 -07:00
eventq.hh event: Allow EventWrapper to take an object reference 2010-04-18 13:23:24 -07:00
fault.hh Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. 2010-09-13 19:26:03 -07:00
faults.cc ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
faults.hh Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. 2010-09-13 19:26:03 -07:00
init.cc init: don't build files that centralize python and swig code 2010-09-09 14:15:42 -07:00
init.hh init: don't build files that centralize python and swig code 2010-09-09 14:15:42 -07:00
insttracer.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
InstTracer.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
main.cc libm5: Create a libm5 static library for embedding m5. 2008-08-03 18:19:54 -07:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
process.cc sim: revamp unserialization procedure 2010-08-17 05:17:06 -07:00
process.hh sim: revamp unserialization procedure 2010-08-17 05:17:06 -07:00
Process.py process: separate stderr from stdout 2008-07-23 14:41:34 -07:00
process_impl.hh Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. 2010-09-13 19:26:03 -07:00
pseudo_inst.cc tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
pseudo_inst.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
root.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
Root.py misc: add some AMD copyright notices 2010-08-17 05:49:05 -07:00
SConscript ARM: Add checkpointing support 2010-11-08 13:58:25 -06:00
serialize.cc Compiler: Fixes for GCC 4.5. 2010-08-23 11:18:39 -05:00
serialize.hh sim: revamp unserialization procedure 2010-08-17 05:17:06 -07:00
sim_events.cc sim: fold StartupCallback into SimObject 2010-07-05 21:39:38 -07:00
sim_events.hh eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
sim_exit.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
sim_object.cc misc: add some AMD copyright notices 2010-08-17 05:49:05 -07:00
sim_object.hh misc: add some AMD copyright notices 2010-08-17 05:49:05 -07:00
sim_object_params.hh eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
simulate.cc includes: sort includes again 2009-05-17 14:34:52 -07:00
simulate.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
stat_control.cc stats: make simTicks and simFreq accessible from stats.hh 2010-04-18 13:23:25 -07:00
stat_control.hh Get rid of the Statistics and Statreset ParamContexts, and 2007-02-17 22:52:32 -08:00
stats.hh stats: make simTicks and simFreq accessible from stats.hh 2010-04-18 13:23:25 -07:00
syscall_emul.cc ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
syscall_emul.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
syscallreturn.hh includes: use base/types.hh not inttypes.h or stdint.h 2009-05-17 14:34:51 -07:00
system.cc ARM: Add checkpointing support 2010-11-08 13:58:25 -06:00
system.hh ARM: Add checkpointing support 2010-11-08 13:58:25 -06:00
System.py scons: use code_formatter wherever we can in the build system 2010-09-09 14:15:41 -07:00
tlb.cc Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. 2010-09-13 19:26:03 -07:00
tlb.hh Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. 2010-09-13 19:26:03 -07:00
vptr.hh Remove delVirtPort() and make getVirtPort() only return cached version. 2008-07-01 10:25:07 -04:00